Datasheet LTC3830, LTC3830-1 (Analog Devices) - 10

LTC3830/LTC3830-1
U U W U APPLICATIO S I FOR ATIO
The RDS(ON) of Q1 usually increases with temperature. To operation of the current limit circuit, PVCC1 must be at keep the current limit threshold constant, the internal least 2.5V above VCC when G1 is high. PVCC1 can go low 12µA sink current at IMAX is designed with a positive when G1 is low, allowing the use of an external charge temperature coefficient to provide first order correction pump to power PVCC1. for the temperature coefficient of RDS(ON)Q1.
Oscillator Frequency
In order for the current limit circuit to operate properly and to obtain a reasonably accurate current limit threshold, the The LTC3830 includes an onboard current controlled I oscillator that typically free-runs at 200kHz. The oscillator IMAX and IFB pins must be Kelvin sensed at Q1’s drain and source pins. In addition, connect a 0.1µF decoupling frequency can be adjusted by forcing current into or out of capacitor across R the FREQSET pin. With the pin floating, the oscillator runs IMAX to filter switching noise. Other- wise, noise spikes or ringing at Q1’s source can cause the at about 200kHz. Every additional 1µA of current into/out actual current limit to be greater than the desired current of the FREQSET pin decreases/increases the frequency by limit set point. Due to switching noise and variation of 10kHz. The pin is internally servoed to 1.265V, connecting R a 50k resistor from FREQSET to ground forces 25 DS(ON), the actual current limit trip point is not highly µA out accurate. The current limiting circuitry is primarily meant of the pin, causing the internal oscillator to run at approxi- to prevent damage to the power supply circuitry during mately 450kHz. Forcing an external 10µA current into fault conditions. The exact current level where the limiting FREQSET cuts the internal frequency to 100kHz. An inter- circuit begins to take effect will vary from unit to unit as the nal clamp prevents the oscillator from running slower than R about 50kHz. Tying FREQSET to V DS(ON) of Q1 varies. Typically, RDS(ON) varies as much as CC forces the chip to run ±40% and with ±25% variation on the LTC3830’s I at this minimum speed. The LTC3830-1 and the 8-lead MAX current, this can give a ±65% variation on the current limit LTC3830 do not have this frequency adjustment function. threshold.
Shutdown
The RDS(ON) is high if the VGS applied to the MOSFET is low. This occurs during power up, when PV The LTC3830 includes a low power shutdown mode, CC1 is ramping up. To prevent the high R controlled by the logic at the SHDN pin. A high at SHDN DS(ON) from activating the current limit, the LTC3830 disables the current limit circuit if allows the part to operate normally. A low level at SHDN for PV more than 100µs forces the LTC3830 into shutdown CC1 is less than 2.5V above VCC. To ensure proper mode. In this mode, all internal switching stops, the COMP VIN and SS pins pull to ground and Q1 and Q2 turn off. The LTC3830 supply current drops to <10µA, although off- LTC3830 + RIMAX 0.1µF CIN state leakage in the external MOSFETs may cause the total + 12 VIN current to be some what higher, especially at elevated I 12µA MAX temperatures. If SHDN returns high, the LTC3830 reruns CC G1 Q1 IFB 1k LO a soft-start cycle and resumes normal operation. The – 13 VOUT + LTC3830-1 does not have this shutdown function. G2 Q2 COUT 3830 F04
Figure 4. Current Limit Setting
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