Datasheet LTC3835-1 (Analog Devices) - 10

LTC3835-1
OPERATION (Refer to Functional Diagram) Light Load Current Operation (Burst Mode Operation,
Mode operation. However, continuous operation has the
Pulse-Skipping, or Continuous Conduction)
advantages of lower output ripple and less interference
(PLLIN/MODE Pin)
to audio circuitry. In forced continuous mode, the output ripple is independent of load current. The LTC3835-1 can be enabled to enter high effi ciency Burst Mode operation, constant-frequency pulse-skipping When the PLLIN/MODE pin is connected for pulse-skip- mode, or forced continuous conduction mode at low load ping mode or clocked by an external clock source to currents. To select Burst Mode operation, tie the PLLIN/ use the phase-locked loop (see Frequency Selection and MODE pin to a DC voltage below 0.8V (e.g., SGND). To Phase-Locked Loop section), the LTC3835-1 operates in select forced continuous operation, tie the PLLIN/MODE PWM pulse-skipping mode at light loads. In this mode, pin to INTVCC. To select pulse-skipping mode, tie the constant-frequency operation is maintained down to ap- PLLIN/MODE pin to a DC voltage greater than 0.8V and proximately 1% of designed maximum output current. less than INTVCC – 0.5V. At very light loads, the current comparator ICMP may remain tripped for several cycles and force the external top When the LTC3835-1 is enabled for Burst Mode operation, MOSFET to stay off for the same number of cycles (i.e., the peak current in the inductor is set to approximately skipping pulses). The inductor current is not allowed to one-tenth of the maximum sense voltage even though the reverse (discontinuous operation). This mode, like forced voltage on the ITH pin indicates a lower value. If the aver- continuous operation, exhibits low output ripple as well as age inductor current is lower than the load current, the low audio noise and reduced RF interference as compared error amplifi er EA will decrease the voltage on the ITH pin. to Burst Mode operation. It provides higher low current When the ITH voltage drops below 0.4V, the internal sleep effi ciency than forced continuous mode, but not nearly as signal goes high (enabling “sleep” mode) and both external high as Burst Mode operation. MOSFETs are turned off. The ITH pin is then disconnected from the output of the EA and “parked” at 0.425V.
Frequency Selection and Phase-Locked Loop
In sleep mode, much of the internal circuitry is turned off,
(PLLLPF and PLLIN/MODE Pins)
reducing the quiescent current that the LTC3835-1 draws The selection of switching frequency is a tradeoff between to only 80μA. In sleep mode, the load current is supplied effi ciency and component size. Low frequency opera- by the output capacitor. As the output voltage decreases, tion increases effi ciency by reducing MOSFET switching the EA’s output begins to rise. When the output voltage losses, but requires larger inductance and/or capacitance drops enough, the ITH pin is reconnected to the output to maintain low output ripple voltage. of the EA, the sleep signal goes low, and the controller resumes normal operation by turning on the top external The switching frequency of the LTC3835-1’s controllers MOSFET on the next cycle of the internal oscillator. can be selected using the PLLLPF pin. When the LTC3835-1 is enabled for Burst Mode operation, If the PLLIN/MODE pin is not being driven by an external clock the inductor current is not allowed to reverse. The reverse source, the PLLLPF pin can be fl oated, tied to INTVCC, or tied current comparator (IR) turns off the bottom external to SGND to select 400kHz, 530kHz or 250kHz, respectively. MOSFET just before the inductor current reaches zero, A phase-locked loop (PLL) is available on the LTC3835-1 preventing it from reversing and going negative, thus to synchronize the internal oscillator to an external clock operating in discontinuous operation. source that is connected to the PLLIN/MODE pin. In this In forced continuous operation, the inductor current is case, a series R-C should be connected between the allowed to reverse at light loads or under large transient PLLLPF pin and SGND to serve as the PLL’s loop fi lter. conditions. The peak inductor current is determined by the The LTC3835-1 phase detector adjusts the voltage on the voltage on the I PLLLPF pin to align the turn-on of the external top MOSFET TH pin, just as in normal operation. In this mode, the effi ciency at light loads is lower than in Burst to the rising edge of the synchronizing signal. 38351fc 10