Datasheet LTC3856 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 2-Phase Synchronous Step-Down DC/DC Controller with Diffamp |
| Pages / Page | 40 / 10 — pin FuncTions (TSSOP/QFN) EXTVCC (Pin 28/Pin 20):. TG1, TG2 (Pins 35, … |
| File Format / Size | PDF / 840 Kb |
| Document Language | English |
pin FuncTions (TSSOP/QFN) EXTVCC (Pin 28/Pin 20):. TG1, TG2 (Pins 35, 23/Pins 25, 17):. INTVCC (Pin 29/Pin 21):
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Text Version of Document
LTC3856
pin FuncTions (TSSOP/QFN) EXTVCC (Pin 28/Pin 20):
External Power Input to an Inter- the sources of the bottom N-channel MOSFETs, the (–) nal Switch Connected to INTVCC. This switch closes and terminal of CVCC and the (–) terminal of CIN. All small-signal supplies the IC power, bypassing the internal low dropout components and compensation components should also regulator, whenever EXTVCC is higher than 4.7V. Do not connect to this ground. exceed 6V on this pin and ensure VIN > VEXTVCC at all times.
TG1, TG2 (Pins 35, 23/Pins 25, 17):
Top Gate Driver
INTVCC (Pin 29/Pin 21):
Internal 5V Regulator Output. The Outputs. These are the outputs of floating drivers with control circuits are powered from this voltage. Decouple a voltage swing equal to INTVCC superimposed on the this pin to PGND with a minimum of 4.7µF low ESR tan- switch nodes voltages. talum or ceramic capacitor.
SW1, SW2 (Pins 36, 22/Pins 26, 16):
Switch Node Con-
VIN (Pin 30/Pin 22):
Main Input Supply. Decouple this pin nections to Inductors. Voltage swing at these pins is from a to PGND with a capacitor (0.1µF to 1µF). Schottky diode (external) voltage drop below ground to VIN.
BG1, BG2 (Pins 31, 27/Pins 23, 19):
Bottom Gate Driver
CLKOUT (Pin 37/Pin 27):
Clock output with phase change- Outputs. These pins drive the gates of the bottom N-channel able by PHASMD to enable usage of multiple LTC3856 ICs MOSFETs between INTVCC and PGND. in multiphase systems.
PGND1, PGND2 (Pins 32, 26) TSSOP Package:
Power
PLLIN (Pin 38/Pin 28):
External Synchronization Pin. A Ground Pin. Connect this pin closely to the sources of the clock on the pin synchronizes the internal oscillator with bottom N-channel MOSFETs, the (–) terminal of CVCC and the clock on this pin. the (–) terminal of CIN.
SGND (Exposed Pad Pin 39) TSSOP Package:
The ex-
BOOST1, BOOST2 (Pins 33, 24/Pins 24, 18):
Boosted posed pad must be soldered to PCB ground for electrical Floating Driver Supplies. The (+) terminal of the boot- connection and rated thermal performance. strap capacitors connect to these pins. These pins swing from a diode voltage drop below INTVCC up to VIN + INTVCC.
SGND/PGND (Exposed Pad Pin 33) QFN Package:
Signal Ground and Power Ground. Connect this pin closely to 3856fa 10 For more information www.linear.com/LTC3856 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions FUNCTIONAL Diagram Operation Applications Information Typical Application Typical Application Related Parts
pin FuncTions (TSSOP/QFN) EXTVCC (Pin 28/Pin 20):
External Power Input to an Inter- the sources of the bottom N-channel MOSFETs, the (–) nal Switch Connected to INTVCC. This switch closes and terminal of CVCC and the (–) terminal of CIN. All small-signal supplies the IC power, bypassing the internal low dropout components and compensation components should also regulator, whenever EXTVCC is higher than 4.7V. Do not connect to this ground. exceed 6V on this pin and ensure VIN > VEXTVCC at all times.
TG1, TG2 (Pins 35, 23/Pins 25, 17):
Top Gate Driver
INTVCC (Pin 29/Pin 21):
Internal 5V Regulator Output. The Outputs. These are the outputs of floating drivers with control circuits are powered from this voltage. Decouple a voltage swing equal to INTVCC superimposed on the this pin to PGND with a minimum of 4.7µF low ESR tan- switch nodes voltages. talum or ceramic capacitor.
SW1, SW2 (Pins 36, 22/Pins 26, 16):
Switch Node Con-
VIN (Pin 30/Pin 22):
Main Input Supply. Decouple this pin nections to Inductors. Voltage swing at these pins is from a to PGND with a capacitor (0.1µF to 1µF). Schottky diode (external) voltage drop below ground to VIN.
BG1, BG2 (Pins 31, 27/Pins 23, 19):
Bottom Gate Driver
CLKOUT (Pin 37/Pin 27):
Clock output with phase change- Outputs. These pins drive the gates of the bottom N-channel able by PHASMD to enable usage of multiple LTC3856 ICs MOSFETs between INTVCC and PGND. in multiphase systems.
PGND1, PGND2 (Pins 32, 26) TSSOP Package:
Power
PLLIN (Pin 38/Pin 28):
External Synchronization Pin. A Ground Pin. Connect this pin closely to the sources of the clock on the pin synchronizes the internal oscillator with bottom N-channel MOSFETs, the (–) terminal of CVCC and the clock on this pin. the (–) terminal of CIN.
SGND (Exposed Pad Pin 39) TSSOP Package:
The ex-
BOOST1, BOOST2 (Pins 33, 24/Pins 24, 18):
Boosted posed pad must be soldered to PCB ground for electrical Floating Driver Supplies. The (+) terminal of the boot- connection and rated thermal performance. strap capacitors connect to these pins. These pins swing from a diode voltage drop below INTVCC up to VIN + INTVCC.
SGND/PGND (Exposed Pad Pin 33) QFN Package:
Signal Ground and Power Ground. Connect this pin closely to 3856fa 10 For more information www.linear.com/LTC3856 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions FUNCTIONAL Diagram Operation Applications Information Typical Application Typical Application Related Parts
