Datasheet LTC3588-1 (Analog Devices) - 8

LTC3588-1
OPERATION
The LTC3588-1 is an ultralow quiescent current power
Internal Rail Generation
supply designed specifically for energy harvesting and/or Two internal rails, CAP and V low current step-down applications. The part is designed to IN2, are generated from VIN and are used to drive the high side PMOS and low side NMOS interface directly to a piezoelectric or alternative A/C power of the buck converter, respectively. Additionally the V source, rectify a voltage waveform and store harvested IN2 rail serves as logic high for output voltage select bits D0 energy on an external capacitor, bleed off any excess power and D1. The V via an internal shunt regulator, and maintain a regulated IN2 rail is regulated at 4.8V above GND while the CAP rail is regulated at 4.8V below V output voltage by means of a nanopower high efficiency IN. These are not intended to be used as external rails. Bypass capacitors synchronous buck regulator. are connected to the CAP and VIN2 pins to serve as energy
Internal Bridge Rectifier
reservoirs for driving the buck switches. When VIN is below 4.8V, VIN2 is equal to VIN and CAP is held at GND. Figure 1 The LTC3588-1 has an internal full-wave bridge rectifier shows the ideal VIN, VIN2 and CAP relationship. accessible via the differential PZ1 and PZ2 inputs that rectifies AC inputs such as those from a piezoelectric 18 element. The rectified output is stored on a capacitor at 16 the VIN pin and can be used as an energy reservoir for the 14 buck converter. The low-loss bridge rectifier has a total 12 VIN drop of about 400mV with typical piezo generated currents 10 (~10µA). The bridge is capable of carrying up to 50mA. TAGE (V) 8 One side of the bridge can be operated as a single-ended VOL 6 V DC input. PZ1 and PZ2 should never be shorted together IN2 4 when the bridge is in use. 2 CAP
Undervoltage Lockout (UVLO)
0 0 5 10 15 VIN (V) When the voltage on VIN rises above the UVLO rising 35881 F01 threshold the buck converter is enabled and charge is
Figure 1. Ideal VIN, VIN2 and CAP Relationship
transferred from the input capacitor to the output capaci- tor. A wide (~1V) UVLO hysteresis window is employed
Buck Operation
with a lower threshold approximately 300mV above the The buck regulator uses a hysteretic voltage algorithm to selected regulated output voltage to prevent short cycling control the output through internal feedback from the V during buck power-up. When the input capacitor voltage OUT sense pin. The buck converter charges an output capaci- is depleted below the UVLO falling threshold the buck tor through an inductor to a value slightly higher than the converter is disabled. Extremely low quiescent current regulation point. It does this by ramping the inductor current (450nA typical) in UVLO allows energy to accumulate on up to 260mA through an internal PMOS switch and then the input capacitor in situations where energy must be ramping it down to 0mA through an internal NMOS switch. harvested from low power sources. This efficiently delivers energy to the output capacitor. The ramp rate is determined by VIN, VOUT, and the inductor value. If the input voltage falls below the UVLO falling threshold 35881fc 8 For more information www.linear.com/LTC3588-1 Document Outline Description Typical Application Absolute Maximum Ratings Pin Configuration Electrical Characteristics Pin Functions Operation Applications Information Typical Application Related Parts