Datasheet AD9684 (Analog Devices) - 5

AD9684 Data Sheet SPECIFICATIONS DC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (500 MSPS), 1.7 V p-p full-scale differential input, 1.0 V internal reference, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted.
Table 1. Parameter Temperature Min Typ Max Unit
RESOLUTION Full 14 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error Full −0.3 0 +0.3 % FSR Offset Matching Full 0 +0.3 % FSR Gain Error Full −6.5 0 +6.5 % FSR Gain Matching Full 0 +5.0 % FSR Differential Nonlinearity (DNL) Full −0.6 ±0.5 +0.7 LSB Integral Nonlinearity (INL) Full −4.5 ±2.5 +5.0 LSB TEMPERATURE DRIFT Offset Error 25°C ±3 ppm/°C Gain Error 25°C −39 ppm/°C INTERNAL VOLTAGE REFERENCE Full 1.0 V INPUT-REFERRED NOISE VREF = 1.0 V 25°C 2.63 LSB rms ANALOG INPUTS Differential Input Voltage Range (Programmable) Full 1.46 2.06 2.06 V p-p Common-Mode Voltage (VCM) 25°C 2.05 V Differential Input Capacitance1 25°C 1.5 pF Analog Input Full Power Bandwidth 25°C 2 GHz POWER SUPPLY AVDD1 Full 1.22 1.25 1.28 V AVDD2 Full 2.44 2.50 2.56 V AVDD3 Full 3.2 3.3 3.4 V DVDD Full 1.22 1.25 1.28 V DRVDD Full 1.22 1.25 1.28 V SPIVDD Full 1.22 1.8 3.4 V IAVDD1 Full 448 503 mA IAVDD2 Full 396 455 mA IAVDD3 Full 103 124 mA IDVDD Full 108 127 mA IDRVDD Full 106 119 mA ISPIVDD Full 2 6 mA POWER CONSUMPTION Total Power Dissipation2 Full 2.2 W Power-Down Dissipation Full 710 mW Standby Full 1.0 W 1 Differential capacitance is measured between the VIN+x and VIN−x pins (x = A or B). 2 Parallel interleaved LVDS mode. The power dissipation on DRVDD changes with the output data mode used. Rev. 0 | Page 4 of 64 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjustment Clock Fine Delay Adjustment Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR DIGITAL DOWNCONVERTERS (DDCs) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION BLOCK DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS DIGITAL OUTPUTS Timing Data Clock Output ADC OVERRANGE MULTICHIP SYNCHRONIZATION SYNC± SETUP AND HOLD WINDOW MONITOR TEST MODES ADC TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE