Datasheet AD7124-8 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | 8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference |
| Pages / Page | 93 / 3 — AD7124-8. Data Sheet. TABLE OF CONTENTS |
| Revision | E |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
AD7124-8. Data Sheet. TABLE OF CONTENTS
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AD7124-8 Data Sheet TABLE OF CONTENTS
Features .. 1 Calibration ... 51 Applications ... 1 Span and Offset Limits .. 52 Functional Block Diagram .. 1 System Synchronization .. 53 Revision History ... 3 Digital Filter .. 54 General Description ... 4 Sinc4 Filter ... 54 Specifications ... 5 Sinc3 Filter ... 56 Timing Characteristics .. 10 Fast Settling Mode (Sinc4 + Sinc1 Filter) .. 58 Absolute Maximum Ratings .. 13 Fast Settling Mode (Sinc3 + Sinc1 Filter) .. 60 Thermal Resistance .. 13 Post Filters ... 62 ESD Caution .. 13 Summary of Filter Options ... 65 Pin Configuration and Function Descriptions ... 14 Diagnostics .. 66 Terminology .. 17 Signal Chain Check .. 66 Typical Performance Characteristics ... 18 Reference Detect ... 66 RMS Noise and Resolution .. 27 Calibration, Conversion, and Saturation Errors .. 66 Full Power Mode ... 27 Overvoltage/Undervoltage Detection ... 66 Mid Power Mode .. 30 Power Supply Monitors ... 67 Low Power Mode .. 33 LDO Monitoring .. 67 Getting Started .. 36 MCLK Counter ... 67 Overview .. 36 SPI SCLK Counter .. 67 Power Supplies .. 37 SPI Read/Write Errors ... 68 Digital Communication ... 37 SPI_IGNORE Error ... 68 Configuration Overview ... 39 Checksum Protection .. 68 ADC Circuit Information .. 44 Memory Map Checksum Protection ... 68 Analog Input Channel ... 44 ROM Checksum Protection .. 69 External Impedance when using a Gain of 1 .. 45 Burnout Currents ... 70 Programmable Gain Array (PGA) ... 46 Temperature Sensor ... 70 Reference ... 46 Grounding and Layout .. 71 Bipolar/Unipolar Configuration .. 46 Applications Information .. 72 Data Output Coding .. 47 Temperature Measurement Using a Thermocouple .. 72 Excitation Currents .. 47 Temperature Measurement Using an RTD ... 73 Bridge Power-Down Switch .. 47 Flowmeter .. 75 Logic Outputs .. 47 On-Chip Registers .. 77 Bias Voltage Generator .. 48 Communications Register ... 78 Clock .. 48 Status Register ... 78 Power Modes ... 48 ADC_CONTROL Register ... 79 Standby and Power-Down Modes .. 48 Data Register ... 81 Digital Interface .. 49 IO_CONTROL_1 Register.. 81 DATA_STATUS .. 51 IO_CONTROL_2 Register.. 83 Serial Interface Reset (DOUT_RDY_DEL and CS_EN Bits) 51 ID Register... 84 Reset ... 51 Error Register .. 84 Rev. D | Page 2 of 92 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION FULL POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) MID POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) LOW POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) GETTING STARTED OVERVIEW Power Modes Analog Inputs Multiplexer Reference Programmable Gain Array (PGA) Burnout Currents Σ-Δ ADC and Filter Channel Sequencer Per Channel Configuration Serial Interface Clock Temperature Sensor Digital Outputs Calibration Excitation Currents Bias Voltage Bridge Power Switch (PSW) Diagnostics POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Configuration Registers Filter Registers Offset Registers Gain Registers Diagnostics ADC Control Register Understanding Configuration Flexibility ADC CIRCUIT INFORMATION ANALOG INPUT CHANNEL EXTERNAL IMPEDANCE WHEN USING A GAIN OF 1 PROGRAMMABLE GAIN ARRAY (PGA) REFERENCE BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING EXCITATION CURRENTS BRIDGE POWER-DOWN SWITCH LOGIC OUTPUTS BIAS VOLTAGE GENERATOR CLOCK POWER MODES STANDBY AND POWER-DOWN MODES DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read Mode DATA_STATUS SERIAL INTERFACE RESET (DOUT__DEL AND _EN BITS) RESET CALIBRATION SPAN AND OFFSET LIMITS SYSTEM SYNCHRONIZATION DIGITAL FILTER SINC4 FILTER Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sequencer Sinc4 50 Hz and 60 Hz Rejection SINC3 FILTER Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sequencer Sinc3 50 Hz and 60 Hz Rejection FAST SETTLING MODE (SINC4 + SINC1 FILTER) Output Data Rate and Settling Time, Sinc4 + Sinc1 Filter Sequencer 50 Hz and 60 Hz Rejection, Sinc4 + Sinc1 Filter FAST SETTLING MODE (SINC3 + SINC1 FILTER) Output Data Rate and Settling Time, Sinc3 + Sinc1 Filter Sequencer 50 Hz and 60 Hz Rejection, Sinc3 + Sinc1 Filter POST FILTERS SUMMARY OF FILTER OPTIONS DIAGNOSTICS SIGNAL CHAIN CHECK REFERENCE DETECT CALIBRATION, CONVERSION, AND SATURATION ERRORS OVERVOLTAGE/UNDERVOLTAGE DETECTION POWER SUPPLY MONITORS LDO MONITORING Power Supply Monitor LDO Capacitor Detect MCLK COUNTER SPI SCLK COUNTER SPI READ/WRITE ERRORS SPI_IGNORE ERROR CHECKSUM PROTECTION MEMORY MAP CHECKSUM PROTECTION ROM CHECKSUM PROTECTION CRC Calculation Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) BURNOUT CURRENTS TEMPERATURE SENSOR GROUNDING AND LAYOUT APPLICATIONS INFORMATION TEMPERATURE MEASUREMENT USING A THERMOCOUPLE TEMPERATURE MEASUREMENT USING AN RTD FLOWMETER ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER ADC_CONTROL REGISTER DATA REGISTER IO_CONTROL_1 REGISTER IO_CONTROL_2 REGISTER ID REGISTER ERROR REGISTER ERROR_EN REGISTER MCLK_COUNT REGISTER CHANNEL REGISTERS CONFIGURATION REGISTERS FILTER REGISTERS OFFSET REGISTERS GAIN REGISTERS OUTLINE DIMENSIONS ORDERING GUIDE
AD7124-8 Data Sheet TABLE OF CONTENTS
Features .. 1 Calibration ... 51 Applications ... 1 Span and Offset Limits .. 52 Functional Block Diagram .. 1 System Synchronization .. 53 Revision History ... 3 Digital Filter .. 54 General Description ... 4 Sinc4 Filter ... 54 Specifications ... 5 Sinc3 Filter ... 56 Timing Characteristics .. 10 Fast Settling Mode (Sinc4 + Sinc1 Filter) .. 58 Absolute Maximum Ratings .. 13 Fast Settling Mode (Sinc3 + Sinc1 Filter) .. 60 Thermal Resistance .. 13 Post Filters ... 62 ESD Caution .. 13 Summary of Filter Options ... 65 Pin Configuration and Function Descriptions ... 14 Diagnostics .. 66 Terminology .. 17 Signal Chain Check .. 66 Typical Performance Characteristics ... 18 Reference Detect ... 66 RMS Noise and Resolution .. 27 Calibration, Conversion, and Saturation Errors .. 66 Full Power Mode ... 27 Overvoltage/Undervoltage Detection ... 66 Mid Power Mode .. 30 Power Supply Monitors ... 67 Low Power Mode .. 33 LDO Monitoring .. 67 Getting Started .. 36 MCLK Counter ... 67 Overview .. 36 SPI SCLK Counter .. 67 Power Supplies .. 37 SPI Read/Write Errors ... 68 Digital Communication ... 37 SPI_IGNORE Error ... 68 Configuration Overview ... 39 Checksum Protection .. 68 ADC Circuit Information .. 44 Memory Map Checksum Protection ... 68 Analog Input Channel ... 44 ROM Checksum Protection .. 69 External Impedance when using a Gain of 1 .. 45 Burnout Currents ... 70 Programmable Gain Array (PGA) ... 46 Temperature Sensor ... 70 Reference ... 46 Grounding and Layout .. 71 Bipolar/Unipolar Configuration .. 46 Applications Information .. 72 Data Output Coding .. 47 Temperature Measurement Using a Thermocouple .. 72 Excitation Currents .. 47 Temperature Measurement Using an RTD ... 73 Bridge Power-Down Switch .. 47 Flowmeter .. 75 Logic Outputs .. 47 On-Chip Registers .. 77 Bias Voltage Generator .. 48 Communications Register ... 78 Clock .. 48 Status Register ... 78 Power Modes ... 48 ADC_CONTROL Register ... 79 Standby and Power-Down Modes .. 48 Data Register ... 81 Digital Interface .. 49 IO_CONTROL_1 Register.. 81 DATA_STATUS .. 51 IO_CONTROL_2 Register.. 83 Serial Interface Reset (DOUT_RDY_DEL and CS_EN Bits) 51 ID Register... 84 Reset ... 51 Error Register .. 84 Rev. D | Page 2 of 92 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION FULL POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) MID POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) LOW POWER MODE Sinc4 Sinc3 Post Filters Fast Settling Filter (Sinc4 + Sinc1) Fast Settling Filter (Sinc3 + Sinc1) GETTING STARTED OVERVIEW Power Modes Analog Inputs Multiplexer Reference Programmable Gain Array (PGA) Burnout Currents Σ-Δ ADC and Filter Channel Sequencer Per Channel Configuration Serial Interface Clock Temperature Sensor Digital Outputs Calibration Excitation Currents Bias Voltage Bridge Power Switch (PSW) Diagnostics POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Configuration Registers Filter Registers Offset Registers Gain Registers Diagnostics ADC Control Register Understanding Configuration Flexibility ADC CIRCUIT INFORMATION ANALOG INPUT CHANNEL EXTERNAL IMPEDANCE WHEN USING A GAIN OF 1 PROGRAMMABLE GAIN ARRAY (PGA) REFERENCE BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING EXCITATION CURRENTS BRIDGE POWER-DOWN SWITCH LOGIC OUTPUTS BIAS VOLTAGE GENERATOR CLOCK POWER MODES STANDBY AND POWER-DOWN MODES DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read Mode DATA_STATUS SERIAL INTERFACE RESET (DOUT__DEL AND _EN BITS) RESET CALIBRATION SPAN AND OFFSET LIMITS SYSTEM SYNCHRONIZATION DIGITAL FILTER SINC4 FILTER Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sequencer Sinc4 50 Hz and 60 Hz Rejection SINC3 FILTER Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sequencer Sinc3 50 Hz and 60 Hz Rejection FAST SETTLING MODE (SINC4 + SINC1 FILTER) Output Data Rate and Settling Time, Sinc4 + Sinc1 Filter Sequencer 50 Hz and 60 Hz Rejection, Sinc4 + Sinc1 Filter FAST SETTLING MODE (SINC3 + SINC1 FILTER) Output Data Rate and Settling Time, Sinc3 + Sinc1 Filter Sequencer 50 Hz and 60 Hz Rejection, Sinc3 + Sinc1 Filter POST FILTERS SUMMARY OF FILTER OPTIONS DIAGNOSTICS SIGNAL CHAIN CHECK REFERENCE DETECT CALIBRATION, CONVERSION, AND SATURATION ERRORS OVERVOLTAGE/UNDERVOLTAGE DETECTION POWER SUPPLY MONITORS LDO MONITORING Power Supply Monitor LDO Capacitor Detect MCLK COUNTER SPI SCLK COUNTER SPI READ/WRITE ERRORS SPI_IGNORE ERROR CHECKSUM PROTECTION MEMORY MAP CHECKSUM PROTECTION ROM CHECKSUM PROTECTION CRC Calculation Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) BURNOUT CURRENTS TEMPERATURE SENSOR GROUNDING AND LAYOUT APPLICATIONS INFORMATION TEMPERATURE MEASUREMENT USING A THERMOCOUPLE TEMPERATURE MEASUREMENT USING AN RTD FLOWMETER ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER ADC_CONTROL REGISTER DATA REGISTER IO_CONTROL_1 REGISTER IO_CONTROL_2 REGISTER ID REGISTER ERROR REGISTER ERROR_EN REGISTER MCLK_COUNT REGISTER CHANNEL REGISTERS CONFIGURATION REGISTERS FILTER REGISTERS OFFSET REGISTERS GAIN REGISTERS OUTLINE DIMENSIONS ORDERING GUIDE
