Datasheet AD7175-2 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 24-Bit, 250 kSPS, Sigma-Delta ADC with 20 µs Settling and True Rail-to-Rail Buffers |
| Pages / Page | 63 / 5 — Table 1. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit |
| Revision | B |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
Table 1. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit
Model Line for this Datasheet
Text Version of Document
AD7175-2 Data Sheet SPECIFICATIONS AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS, MCLK = internal master clock = 16 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPEED AND PERFORMANCE Output Data Rate (ODR) 5 250,000 SPS No Missing Codes1 Excluding sinc3 filter ≥ 125 kSPS 24 Bits Resolution See Table 6 and Table 7 Noise See Table 6 and Table 7 ACCURACY Integral Nonlinearity (INL) Analog input buffers enabled ±3.5 ±7.8 ppm of FSR Analog input buffers disabled ±1 ±3.5 ppm of FSR Offset Error2 Internal short ±40 µV Offset Drift Internal short ±80 nV/°C Gain Error2 ±35 ±85 ppm of FSR Gain Drift ±0.4 ±0.75 ppm/°C REJECTION Power Supply Rejection AVDD1, AVDD2, VIN = 1 V 95 dB Common-Mode Rejection VIN = 0.1 V At DC 95 dB At 50 Hz, 60 Hz1 20 Hz output data rate (post filter), 120 dB 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Normal Mode Rejection1 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (postfilter) 71 90 dB External clock, 20 SPS ODR (postfilter) 85 90 dB ANALOG INPUTS Differential Input Range VREF = (REF+) − (REF−) ±VREF V Absolute Voltage Limits1 Input Buffers Disabled AVSS − 0.05 AVDD1 + 0.05 V Input Buffers Enabled AVSS AVDD1 V Analog Input Current Input Buffers Disabled Input Current ±48 µA/V Input Current Drift External clock ±0.75 nA/V/°C Internal clock (±2.5% clock) ±4 nA/V/°C Input Buffers Enabled Input Current ±30 nA Input Current Drift AVDD1 − 0.2 V to AVSS + 0.2 V ±75 pA/°C AVDD1 to AVSS ±1 nA/°C Crosstalk 1 kHz input −120 dB INTERNAL REFERENCE 100 nF external capacitor to AVSS Output Voltage REFOUT, with respect to AVSS 2.5 V Initial Accuracy3 REFOUT, TA = 25°C −0.12 +0.12 % of V Temperature Coefficient 0°C to 105°C1 ±2 ±5 ppm/°C −40°C to +105°C1 ±3 ±10 ppm/°C Reference Load Current, ILOAD −10 +10 mA Power Supply Rejection AVDD1, AVDD2, (line regulation) 90 dB Load Regulation ∆VOUT/∆ILOAD 32 ppm/mA Voltage Noise eN, 0.1 Hz to 10 Hz, 2.5 V reference 4.5 µV rms Voltage Noise Density eN, 1 kHz, 2.5 V reference 215 nV/√Hz Rev. B | Page 4 of 62
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPEED AND PERFORMANCE Output Data Rate (ODR) 5 250,000 SPS No Missing Codes1 Excluding sinc3 filter ≥ 125 kSPS 24 Bits Resolution See Table 6 and Table 7 Noise See Table 6 and Table 7 ACCURACY Integral Nonlinearity (INL) Analog input buffers enabled ±3.5 ±7.8 ppm of FSR Analog input buffers disabled ±1 ±3.5 ppm of FSR Offset Error2 Internal short ±40 µV Offset Drift Internal short ±80 nV/°C Gain Error2 ±35 ±85 ppm of FSR Gain Drift ±0.4 ±0.75 ppm/°C REJECTION Power Supply Rejection AVDD1, AVDD2, VIN = 1 V 95 dB Common-Mode Rejection VIN = 0.1 V At DC 95 dB At 50 Hz, 60 Hz1 20 Hz output data rate (post filter), 120 dB 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Normal Mode Rejection1 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (postfilter) 71 90 dB External clock, 20 SPS ODR (postfilter) 85 90 dB ANALOG INPUTS Differential Input Range VREF = (REF+) − (REF−) ±VREF V Absolute Voltage Limits1 Input Buffers Disabled AVSS − 0.05 AVDD1 + 0.05 V Input Buffers Enabled AVSS AVDD1 V Analog Input Current Input Buffers Disabled Input Current ±48 µA/V Input Current Drift External clock ±0.75 nA/V/°C Internal clock (±2.5% clock) ±4 nA/V/°C Input Buffers Enabled Input Current ±30 nA Input Current Drift AVDD1 − 0.2 V to AVSS + 0.2 V ±75 pA/°C AVDD1 to AVSS ±1 nA/°C Crosstalk 1 kHz input −120 dB INTERNAL REFERENCE 100 nF external capacitor to AVSS Output Voltage REFOUT, with respect to AVSS 2.5 V Initial Accuracy3 REFOUT, TA = 25°C −0.12 +0.12 % of V Temperature Coefficient 0°C to 105°C1 ±2 ±5 ppm/°C −40°C to +105°C1 ±3 ±10 ppm/°C Reference Load Current, ILOAD −10 +10 mA Power Supply Rejection AVDD1, AVDD2, (line regulation) 90 dB Load Regulation ∆VOUT/∆ILOAD 32 ppm/mA Voltage Noise eN, 0.1 Hz to 10 Hz, 2.5 V reference 4.5 µV rms Voltage Noise Density eN, 1 kHz, 2.5 V reference 215 nV/√Hz Rev. B | Page 4 of 62
