Datasheet AD7656A-1 (Analog Devices) - 22

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Data Sheet AD7656A-1 t1 CONVST A, t10 CONVST B, t t CONV ACQ CONVST C t BUSY 2 ACQUISITION CONVERSION ACQUISITION CS tQUIET SCLK t t 19 18 t16 t17 t20 DOUT A, t21 DOUT B, DB15 DB14 DB13 DB1 DB0
032
DOUT C
11128- Figure 30. Serial Read Operation Data can also be clocked out using just one DOUT x line, in which
SERIAL READ OPERATION
case, use DOUT A to access the conversion data. To configure Figure 30 shows the timing diagram for reading data from the the AD7656A-1 to operate in this mode, tie DB0/SEL A to AD7656A-1 when the serial interface. The SCLK input signal VDRIVE, and tie DB1/SEL B and DB2/SEL C low. The disadvantage provides the clock source for the serial interface. The CS signal of using only one DOUT x line is that the throughput rate is goes low to access data from the AD7656A-1. The falling edge reduced. Data can be accessed from the AD7656A-1 using one 96-SCLK transfer, three 32-SCLK individual y framed transfers, or of CS takes the bus out of three-state and clocks out the MSB of six 16-SCLK individually framed transfers. Any additional SCLKs the 16-bit conversion result. The ADCs output 16 bits for each applied after this result in an output of al zeros. When using the conversion result; the data stream of the AD7656A-1 consists of 16 bits of conversion data, provided MSB first. serial interface, tie the RD signal low, and leave the unused DOUT x line(s) unconnected. The first bit of the conversion result is valid on the first SCLK fal ing edge after the CS falling edge. The subsequent 15 data Whether one, two, or three data output lines are used, if a particular CONVST x pin is not used in the conversion cycle, bits are clocked out on the rising edge of the SCLK signal. Data all zeros are output in place of the ADC result for the associated is valid on the SCLK falling edge. To access each conversion result, ADCs even though they were not used in the conversion cycle. 16 clock pulses must be provided to the AD7656A-1. Figure 30 This means that if, for example, only CONVST B is pulsed and shows how a 16-SCLK read is used to access the conversion one data output pin is in use, 64 SCLKs are required to access results. the results from V3 and V4; however, only 32 SCLKs are required if two or three data output lines are in use. Rev. 0 | Page 21 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS POWER SUPPLY SEQUENCING THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CONVERTER DETAILS Track-and-Hold Amplifiers Analog Input ADC TRANSFER FUNCTION INTERNAL/EXTERNAL REFERENCE TYPICAL CONNECTION DIAGRAM DRIVING THE ANALOG INPUTS INTERFACE OPTIONS Parallel Interface (SER/PAR/SEL = 0) SOFTWARE SELECTION OF ADCS Changing the Analog Input Range (H/S SEL = 0) Changing the Analog Input Range (H/S SEL = 1) Serial Interface (SER/PAR/SEL = 1) SERIAL READ OPERATION DAISY-CHAIN MODE (DCEN = 1, SER/PAR/SEL = 1) Standby/Partial Power-Down Modes of Operation(SER/PAR/SEL = 0 or SER/PAR/SEL = 1) APPLICATION HINTS LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE