Datasheet AD9683 (Analog Devices) - 5

AD9683 Data Sheet SPECIFICATIONS ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, duty cycle stabilizer enabled, default SPI, unless otherwise noted.
Table 1. AD9683-170 AD9683-250 Parameter Temperature Min Typ Max Min Typ Max Unit
RESOLUTION Full 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±9 ±9 mV Gain Error Full −6.6/−0.3 −5.3/+1.2 %FSR Differential Nonlinearity (DNL) Full ±0.8 ±0.75 LSB 25°C ±0.5 ±0.5 LSB Integral Nonlinearity (INL)1 Full ±1.6 ±2.7 LSB 25°C ±0.8 ±1.5 LSB TEMPERATURE DRIFT Offset Error Full ±7 ±7 ppm/°C Gain Error Full ±13 ±39 ppm/°C INPUT REFERRED NOISE VREF = 1.75 V 25°C 1.38 1.42 LSB rms ANALOG INPUT Input Span Full 1.75 1.75 V p-p Input Capacitance2 Full 2.5 2.5 pF Input Resistance3 Full 20 20 kΩ Input Common-Mode Voltage Full 0.9 0.9 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V Supply Current IAVDD Full 135 151 149 163 mA IDRVDD + IDVDD Full 68 73 92 97 mA POWER CONSUMPTION Sine Wave Input Full 365 403 434 468 mW Standby Power4 Full 221 266 mW Power-Down Power5 Full 9 9 mW 1 Measured with a low input frequency, full-scale sine wave. 2 Input capacitance refers to the effective capacitance between one differential input pin and its complement. 3 Input resistance refers to the effective resistance between one differential input pin and its complement. 4 Standby power is measured with a low input frequency, full-scale sine wave, and the CLK± pins active. Address 0x08 is set to 0x20, and the PDWN pin is asserted. 5 Power-down power is measured with a low input frequency, a full-scale sine wave, RFCLK pulled high, and the CLK± pins active. Address 0x08 is set to 0x00, and the PDWN pin is asserted. Rev. D | Page 4 of 44 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Nyquist Clock Input Options RF Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS JESD204B TRANSMIT TOP LEVEL DESCRIPTION JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lane Before Changing Configuration Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lane After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing ADC OVERRANGE AND GAIN CONTROL ADC Overrange (OR) Gain Switching Fast Threshold Detection (FD) DC CORRECTION (DCC) DC CORRECTION BANDWIDTH DC CORRECTION READBACK DC CORRECTION FREEZE DC CORRECTION ENABLE BITS SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS PDWN Modes (Address 0x08) Output Mode (Address 0x14) SYNCINB±/SYSREF± Control (Address 0x3A) DC Correction Control (Address 0x40) DC Correction Value 0 (Address 0x41) DC Correction Value 1 (Address 0x42) Fast Detect Control (Address 0x45) Fast Detect Upper Threshold (Address 0x47 and Address 0x48) Fast Detect Lower Threshold (Address 0x49 and Address 0x4A) Fast Detect Dwell Time (Address 0x4B and Address  0x4C) JESD204B Quick Configuration (Address 0x5E) JESD204B Link Control 1 (Address 0x5F) JESD204B Link Control 2 (Address 0x60) JESD204B Link Control 3 (Address 0x61) JESD204B Device Identification (DID) Configuration (Address 0x64) JESD204B Bank Identification (BID) Configuration (Address 0x65) JESD204B Lane Identification (LID) Configuration (Address 0x67) JESD204B Scrambler (SCR) and Lane (L) Configuration (Address 0x6E) JESD204B Parameter, F (Address 0x6F, Read Only) JESD204B Parameter, K (Address 0x70) JESD204B Parameter, M (Address 0x71) JESD204B Parameters, N/CS (Address 0x72) JESD204B Parameter, Subclass/N’ (Address 0x73) JESD204B Samples per Converter per Frame Cycle (S) (Address 0x74) JESD204B Parameters HD and CF (Address 0x75) JESD204B Reserved 1 (Address 0x76) JESD204B Reserved 2 (Address 0x77) JESD204B Checksum (Address 0x79) JESD204B Output Driver Control (Address 0x80) JESD204B LMFC Offset (Address 0x8B) JESD204B Preemphasis (Address 0xA8) APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Pad Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE