Datasheet ADAS3022 (Analog Devices) - 6

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Data Sheet ADAS3022 Parameter Test Conditions/Comments Min Typ Max Unit
1 AC Performance Internal reference Signal-to-Noise Ratio (SNR) 90.0 93.0 dB Signal-to-Noise-and-Distortion 89.5 92.5 dB (SINAD) Total Harmonic Distortion −105 dB Spurious-Free Dynamic Range 110 dB (SFDR) INTERNAL REFERENCE REFx Output Voltage TA = 25°C 4.088 4.096 4.104 V REFx Output Current TA = 25°C 250 µA REFx Temperature Drift REFEN = 1 ±5 ppm/°C REFEN = 0 ±1 ppm/°C REFx Line Regulation AVDD = 5 V ± 5% Internal Reference 20 µV/V Buffer Only 4 µV/V REFIN Output Voltage4 TA = 25°C 2.495 2.500 2.505 V Turn-On Settling Time CREFIN, CREF1, CREF2 = 10 µF and 0.1 µF 100 ms EXTERNAL REFERENCE Voltage Range REFx input 4.000 4.096 4.104 V REFIN input (buffered) 2.5 2.505 V Current Drain VREF = 4.096 V 100 µA TEMPERATURE SENSOR Output Voltage TA = 25 °C 275 mV Temperature Sensitivity 800 µV/°C DIGITAL INPUTS Logic Levels VIL VIO > 3 V −0.3 +0.3 × VIO V VIH VIO > 3 V 0.7 × VIO VIO + 0.3 V VIL VIO ≤ 3 V −0.3 +0.1 × VIO V VIH VIO ≤ 3 V 0.9 × VIO VIO + 0.3 V IIL −1 +1 µA IIH −1 +1 µA DIGITAL OUTPUTS5 Data Format Twos complement VOL ISINK = +500 µA 0.4 V VOH ISOURCE = −500 µA VIO − 0.3 V POWER SUPPLIES PD = 0 VIO 1.8 AVDD + 0.3 V AVDD 4.75 5 5.25 V DVDD 4.75 5 5.25 V VDDH6 VDDH > input voltage + 2.5 V 14.25 15 15.75 V VSSH6 VSSH < input voltage − 2.5 V −15.75 −15 −14.25 V IVDDH PGIA gain = 0.16 3.0 3.5 mA PGIA gain = 0.2 3.0 3.5 mA PGIA gain = 0.4 3.5 4.0 mA PGIA gain = 0.8 5.0 5.5 mA PGIA gain = 1.6 8.5 9.5 mA PGIA gain = 3.2 15.5 17.5 mA PGIA gain = 6.4 15.5 17.5 mA All PGIA gains, PD = 1 100 µA Rev. C | Page 5 of 40 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Overview ADAS3022 Operation Transfer Function Typical Application Connection Diagram Analog Inputs Input Structure Programmable Gain Common-Mode Operating Range Fully Differential, Antiphase Signals with a Zero Common Mode Fully Differential, Antiphase Signals with a Nonzero Common Mode Differential, Nonantiphase Signals with a Zero Common Mode Single-Ended Signals with a Nonzero DC Offset (Asymmetrical) Single-Ended Signals with a 0 V DC Offset (Symmetrical) Multiplexer Channel Sequencer Auxiliary Input Channel Driver Amplifier Choice Voltage Reference Output/Input Internal Reference External Reference and Internal Buffer External Reference Reference Decoupling Power Supply Core Supplies High Voltage Supplies Power Dissipation Modes Fully Operational Mode Power-Down Mode Conversion Modes Warp Mode (CMS = 0) Normal Mode (CMS = 1, Default) Digital Interface Conversion Control CNV Rising Edge—Start of a Conversion (SOC) BUSY Falling Edge—End of a Conversion (EOC) Reset and Power-Down (PD) Inputs Serial Data Interface CPHA Sampling on the SCK Falling Edge Sampling on the SCK Rising Edge (Alternate Edge) CFG Readback General Considerations Data Access During Conversion—Maximum Throughput General Timing Configuration Register On Demand Conversion Mode Channel Sequencer Details INx and COM Inputs (MUX = 1, TEMPB = 1) INx and COM Inputs with AUX Inputs (MUX = 0, TEMPB = 1) INx and COM Inputs with Temperature Sensor (MUX = 1, TEMPB = 0) INx and COM Inputs with AUX Inputs and Temperature Sensor (MUX = 0, TEMPB = 0) Sequencer Modes Basic Sequencer Mode (SEQ = 11) Update During Sequence (SEQ = 01) Advanced Sequencer Mode (SEQ = 10) Outline Dimensions Ordering Guide