Datasheet AD9250 (Analog Devices) - 4

AD9250 Data Sheet GENERAL DESCRIPTION
The AD9250 is a dual, 14-bit ADC with sampling speeds of up By default, the ADC output data is routed directly to the two to 250 MSPS. The AD9250 is designed to support communications JESD204B serial output lanes. These outputs are at CML voltage applications where low cost, small size, wide bandwidth, and levels. Four modes support any combination of M = 1 or 2 (single versatility are desired. or dual converters) and L = 1 or 2 (one or two lanes). For dual The ADC cores feature a multistage, differential pipelined ADC mode, data can be sent through two lanes at the maximum architecture with integrated output error correction logic. The sampling rate of 250 MSPS. However, if data is sent through ADC cores feature wide bandwidth inputs supporting a variety one lane, a sampling rate of up to 125 MSPS is supported. of user-selectable input ranges. An integrated voltage reference Synchronization inputs (SYNCINB± and SYSREF±) are provided. eases design considerations. A duty cycle stabilizer is provided Flexible power-down options allow significant power savings, to compensate for variations in the ADC clock duty cycle, allowing when desired. Programmable overrange level detection is the converters to maintain excellent performance. The JESD204B supported for each channel via the dedicated fast detect pins. high speed serial interface reduces board routing requirements Programming for setup and control are accomplished using a and lowers pin count requirements for the receiving device. 3-wire SPI-compatible serial interface. The AD9250 is available in a 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. Rev. E | Page 4 of 45 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Nyquist Clock Input Options RF Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Before Changing Configuration Select Quick Configuration Option Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Additional Digital Output Configuration Options Re-Enable Lanes After Configuration Internal FIFO Timing Optimization Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing ADC Overrange and Gain Control ADC Overrange (OR) Gain Switching Fast Threshold Detection (FDA and FDB) DC Correction DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction (DCC) Enable Bits Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Description Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port SPI Initialization Sequence Outline Dimensions Ordering Guide