Datasheet AD9250 (Analog Devices) - 7

Data Sheet AD9250 AD9250-170 AD9250-250 Parameter1 Temperature Min Typ Max Min Typ Max Unit
TWO-TONE SFDR fIN = 184.12 MHz (−7 dBFS), 187.12 MHz (−7 dBFS) 25°C 87 84 dBc CROSSTALK2 Full 95 95 dB FULL POWER BANDWIDTH3 25°C 1000 1000 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel. 3 Full power bandwidth is the bandwidth of operation determined by where the spectral power of the fundamental frequency is reduced by 3 dB.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p ful -scale input range, DCS enabled, link parameters used were M = 2 and L = 2, unless otherwise noted.
Table 3. Parameter Temperature Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Input CLK± Clock Rate Full 40 625 MHz Logic Compliance CMOS/LVDS/LVPECL Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Full 0.3 3.6 V p-p Input Voltage Range Full AGND AVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full 0 +60 µA Low Level Input Current Full −60 0 µA Input Capacitance Full 4 pF Input Resistance Full 8 10 12 kΩ RF CLOCK INPUT (RFCLK) Input CLK± Clock Rate Full 650 1500 MHz Logic Compliance CMOS/LVDS/LVPECL Internal Bias Full 0.9 V Input Voltage Range Full AGND AVDD V Input Voltage Level High Full 1.2 AVDD V Low Full AGND 0.6 V High Level Input Current Full 0 +150 µA Low Level Input Current Full −150 0 µA Input Capacitance Full 1 pF Input Resistance (AC-Coupled) Full 8 10 12 kΩ SYNCIN INPUT (SYNCINB+/SYNCINB−) Logic Compliance CMOS/LVDS Internal Common-Mode Bias Full 0.9 V Differential Input Voltage Range Full 0.3 3.6 V p-p Input Voltage Range Full DGND DVDD V Input Common-Mode Range Full 0.9 1.4 V High Level Input Current Full −5 +5 µA Low Level Input Current Full −5 +5 µA Input Capacitance Full 1 pF Input Resistance Full 12 16 20 kΩ Rev. E | Page 7 of 45 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Nyquist Clock Input Options RF Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Before Changing Configuration Select Quick Configuration Option Configure Detailed Options Check FCHK, Checksum of JESD204B Interface Parameters Additional Digital Output Configuration Options Re-Enable Lanes After Configuration Internal FIFO Timing Optimization Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing ADC Overrange and Gain Control ADC Overrange (OR) Gain Switching Fast Threshold Detection (FDA and FDB) DC Correction DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction (DCC) Enable Bits Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers Memory Map Register Table Memory Map Register Description Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port SPI Initialization Sequence Outline Dimensions Ordering Guide