Datasheet AD9635 (Analog Devices) - 5

AD9635 Data Sheet AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 2. AD9635-80 AD9635-125 Parameter1 Temp Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz 25°C 71.8 71.5 dBFS fIN = 30.5 MHz 25°C 71.7 71.5 dBFS fIN = 70 MHz Full 70.6 71.2 70.1 71.1 dBFS fIN = 139.5 MHz 25°C 69.9 70.2 dBFS fIN = 200.5 MHz 25°C 68.4 68.9 dBFS SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD) fIN = 9.7 MHz 25°C 71.8 71.5 dBFS fIN = 30.5 MHz 25°C 71.6 71.5 dBFS fIN = 70 MHz Full 70.5 71.2 69.7 71.1 dBFS fIN = 139.5 MHz 25°C 69.6 70.2 dBFS fIN = 200.5 MHz 25°C 68.2 68.7 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 11.6 11.6 Bits fIN = 30.5 MHz 25°C 11.6 11.6 Bits fIN = 70 MHz Full 11.4 11.5 11.3 11.5 Bits fIN = 139.5 MHz 25°C 11.3 11.4 Bits fIN = 200.5 MHz 25°C 11.0 11.1 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 93 92 dBc fIN = 30.5 MHz 25°C 90 93 dBc fIN = 70 MHz Full 82 94 82 93 dBc fIN = 139.5 MHz 25°C 81 92 dBc fIN = 200.5 MHz 25°C 82 83 dBc WORST HARMONIC (SECOND OR THIRD) fIN = 9.7 MHz 25°C −93 −92 dBc fIN = 30.5 MHz 25°C −90 −93 dBc fIN = 70 MHz Full −94 −85 −93 −82 dBc fIN = 139.5 MHz 25°C −81 −92 dBc fIN = 200.5 MHz 25°C −82 −83 dBc WORST OTHER HARMONIC OR SPUR fIN = 9.7 MHz 25°C −96 −95 dBc fIN = 30.5 MHz 25°C −95 −95 dBc fIN = 70 MHz Full −94 −82 −94 −82 dBc fIN = 139.5 MHz 25°C −95 −93 dBc fIN = 200.5 MHz 25°C −92 −89 dBc TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS fIN1 = 70.5 MHz, fIN2 = 72.5 MHz 25°C −92 −92 dBc CROSSTALK2 25°C −97 −97 dB CROSSTALK (OVERRANGE CONDITION)3 25°C −97 −97 dB POWER SUPPLY REJECTION RATIO (PSRR)4 AVDD 25°C 44 43 dB DRVDD 25°C 59 66 dB ANALOG INPUT BANDWIDTH, FULL POWER 25°C 650 650 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Crosstalk is measured at 70 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel. 3 Overrange condition is specified with 3 dB of the full-scale input range. 4 PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the amplitude of the spur voltage over the amplitude of the pin voltage, expressed in decibels (dB). Rev. B | Page 4 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9635-80 AD9635-125 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/PDWN Pin SCLK/DFS Pin CSB Pin RBIAS Pin OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Bits[7:2]—Open Bits[1:0]—Power Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Bits[5:3]—Open Bit 2—Output Invert Bit 1—Open Bit 0—Output Format Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination Bits[3:1]—Open Bit 0—Output Drive Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust Bits[3:0]—Output Clock Phase Adjust Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND GUIDELINES CLOCK STABILITY CONSIDERATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE