Datasheet AD9642 (Analog Devices)

14-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter (ADC) Data Sheet AD9642 FEATURES FUNCTIONAL BLOCK DIAGRAM SNR = 71.0 dBFS at 185 MHz A AVDD AGND DRVDD IN and 250 MSPS SFDR = 83 dBc at 185 MHz AIN and 250 MSPS −152.0 dBFS/Hz input noise at 200 MHz, −1 dBFS A VIN+ IN, 250 MSPS PIPELINE 14 D0±/D1± 14-BIT Total power consumption: 390 mW at 250 MSPS VIN– ADC 1.8 V supply voltages VCM AD9642 PARALLEL DDR LVDS LVDS (ANSI-644 levels) outputs AND D12±/D13± DRIVERS Integer 1-to-8 input clock divider (625 MHz maximum input) Sample rates of up to 250 MSPS DCO± Internal ADC voltage reference REFERENCE Flexible analog input range 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) 1-TO-8 SERIAL PORT CLOCK ADC clock duty cycle stabilizer DIVIDER Serial port control
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Energy saving power-down modes
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SCLK SDIO CSB CLK+ CLK–
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APPLICATIONS
Figure 1.
Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, WCDMA, CDMA2000, GSM, EDGE, LTE I/Q demodulation systems Smart antenna systems General-purpose software radios Ultrasound equipment Broadband data applications GENERAL DESCRIPTION
The AD9642 is a 14-bit analog-to-digital converter (ADC) with Programming for setup and control is accomplished using a sampling speeds of up to 250 MSPS. The AD9642 is designed to 3-wire SPI-compatible serial interface. support communications applications, where low cost, small The AD9642 is available in a 32-lead LFCSP and is specified size, wide bandwidth, and versatility are desired. over the industrial temperature range of −40°C to +85°C. This The ADC core features a multistage, differential pipelined product is protected by a U.S. patent. architecture with integrated output error correction logic. The
PRODUCT HIGHLIGHTS
ADC features wide bandwidth inputs that can support a variety of user-selectable input ranges. An integrated voltage reference 1. Integrated 14-bit, 170 MSPS/210 MSPS/250 MSPS ADC. eases design considerations. A duty cycle stabilizer (DCS) is 2. Operation from a single 1.8 V supply and a separate digital provided to compensate for variations in the ADC clock duty output driver supply accommodating LVDS outputs. cycle, allowing the converter to maintain excellent performance. 3. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 350 MHz. The ADC output data is routed directly to the external 4. 3-pin, 1.8 V SPI port for register programming and readback. 14-bit LVDS output port. 5. Pin compatibility with the AD9634, allowing a simple migra- Flexible power-down options allow significant power savings, tion from 14 bits to 12 bits, and with the AD6672. when desired.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE