Datasheet AD9608 (Analog Devices) - 6
Manufacturer | Analog Devices |
Description | 10-Bit, 125/105 MSPS, 1.8 V Dual Analog-to-Digital Converter |
Pages / Page | 41 / 6 — Data Sheet. AD9608. AC SPECIFICATIONS. Table 2. AD9608-105. AD9608-125. … |
Revision | C |
File Format / Size | PDF / 1.1 Mb |
Document Language | English |
Data Sheet. AD9608. AC SPECIFICATIONS. Table 2. AD9608-105. AD9608-125. Parameter1. Temp. Min. Typ. Max. Unit
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Text Version of Document
Data Sheet AD9608 AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.
Table 2. AD9608-105 AD9608-125 Parameter1 Temp Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE-RATIO (SNR) fIN = 9.7 MHz 25°C 61.7 61.7 dBFS fIN = 30.5 MHz 25°C 61.7 61.7 dBFS fIN = 70 MHz 25°C 61.7 61.7 dBFS Full 61.3 61.3 dBFS fIN = 100 MHz 25°C 61.6 61.6 dBFS fIN = 200 MHz 25°C 61.4 61.4 dBFS SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 9.7 MHz 25°C 61.6 61.6 dBFS fIN = 30.5 MHz 25°C 61.6 61.6 dBFS fIN = 70 MHz 25°C 61.6 61.6 dBFS Full 61.1 61.1 dBFS fIN = 100 MHz 25°C 61.5 61.5 dBFS fIN = 200 MHz 25°C 61.3 61.3 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 9.9 9.9 Bits fIN = 30.5 MHz 25°C 9.9 9.9 Bits fIN = 70 MHz 25°C 9.9 9.9 Bits fIN = 100 MHz 25°C 9.9 9.9 Bits fIN = 200 MHz 25°C 9.9 9.9 Bits WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz 25°C −90 −90 dBc fIN = 30.5 MHz 25°C −89 −89 dBc fIN = 70 MHz 25°C −89 −89 dBc Full −75 −75 dBc fIN = 100 MHz 25°C −89 −89 dBc fIN = 200 MHz 25°C −84 −84 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 85 85 dBc fIN = 30.5 MHz 25°C 85 85 dBc fIN = 70 MHz 25°C 85 85 dBc Full 75 75 dBc fIN = 100 MHz 25°C 85 85 dBc fIN = 200 MHz 25°C 84 84 dBc WORST OTHER (HARMONIC OR SPUR) fIN = 9.7 MHz 25°C −85 −85 dBc fIN = 30.5 MHz 25°C −85 −85 dBc fIN = 70 MHz 25°C −85 −85 dBc Full −75 −75 dBc fIN = 100 MHz 25°C −85 −85 dBc fIN = 200 MHz 25°C −85 −85 dBc TWO-TONE SFDR fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS ) 25°C 82 82 dBc CROSSTALK2 Full −95 −95 dB ANALOG INPUT BANDWIDTH 25°C 650 650 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel. Rev. C | Page 5 of 40 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9608-125 AD9608-105 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) OUTPUT TEST OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Power Modes (Register 0x08) Bits[7:6]—Open Bits[4:2]—Open Bits[1:0]—Internal Power-Down Mode Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode Bits[1:0]—Open Output Mode (Register 0x14) Bits[7:6]—Output Port Logic Type Bit 5—Output Interleave Enable Bit 4—Output Port Disable Bit 3—Open Bit 2—Output Invert Bits[1:0]—Output Format Sync Control (Register 0x3A) Bits[7:3]—Open Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Open Transfer (Register 0xFF) Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) Bit 7—OEB Pin Enable Bits[6:1]—Open Bit 0—SDIO Pull-Down User I/O Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bits[2:0]—Open APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Clock Stability Considerations Exposed Paddle Thermal Heat Slug Recommendations VCM Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE