Datasheet AD9643 (Analog Devices) - 4

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AD9643 Data Sheet ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, unless otherwise noted.
Table 2. AD9643- 170 AD9643- 210 AD9643- 250 Parameter1 Temperature Min Typ Max Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE-RATIO (SNR) fIN = 30 MHz 25°C 72.6 72.6 72.0 dBFS fIN = 90 MHz 25°C 72.2 72.2 71.6 dBFS Full 70.8 70.6 dBFS fIN = 140 MHz 25°C 71.8 71.3 71.2 dBFS fIN = 185 MHz 25°C 71.2 70.6 70.6 dBFS Full 68.8 dBFS fIN = 220 MHz 25°C 70.7 69.9 69.9 dBFS SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 30 MHz 25°C 71.6 71.5 70.9 dBFS fIN = 90 MHz 25°C 71.1 71.2 70.5 dBFS Full 70.4 69.9 dBFS fIN = 140 MHz 25°C 70.5 70.1 69.9 dBFS fIN = 185 MHz 25°C 69.6 69.2 69.4 dBFS Full 67.5 dBFS fIN = 220 MHz 25°C 69.1 68.1 68.8 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 30 MHz 25°C 11.6 11.6 11.5 Bits fIN = 90 MHz 25°C 11.5 11.5 11.4 Bits fIN = 140 MHz 25°C 11.4 11.4 11.3 Bits fIN = 185 MHz 25°C 11.3 11.2 11.2 Bits fIN = 220 MHz 25°C 11.2 11.0 11.1 Bits WORST SECOND OR THIRD HARMONIC fIN = 30 MHz 25°C −95 −90 −90 dBc fIN = 90 MHz 25°C −92 −90 −88 dBc Full −78 −80 dBc fIN = 140 MHz 25°C −88 −88 −86 dBc fIN = 185 MHz 25°C −83 −87 −85 dBc Full −80 dBc fIN = 220 MHz 25°C −83 −85 −85 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 30 MHz 25°C 95 90 90 dBc fIN = 90 MHz 25°C 92 90 88 dBc Full 78 80 dBc fIN = 140 MHz 25°C 88 88 86 dBc fIN = 185 MHz 25°C 83 87 85 dBc Full 80 dBc fIN = 220 MHz 25°C 83 85 85 dBc WORST OTHER (HARMONIC OR SPUR) fIN = 30 MHz 25°C −98 −95 −94 dBc fIN = 90 MHz 25°C −97 −95 −93 dBc Full −78 −80 dBc fIN = 140 MHz 25°C −97 −93 −92 dBc fIN = 185 MHz 25°C −96 −92 −92 dBc Full −80 dBc fIN = 220 MHz 25°C −94 −90 −88 dBc Rev. E | Page 4 of 36 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Voltage Reference Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) ADC Overrange (OR) Channel/Chip Synchronization Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Description Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Buffer Enable Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port Outline Dimensions Ordering Guide