Datasheet AD9613 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 12-bit, 170/210/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) |
| Pages / Page | 38 / 4 — AD9613. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 2/2017—Rev. C to … |
| Revision | D |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
AD9613. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 2/2017—Rev. C to Rev. D. 1/2013—Rev. B to Rev. C. /2011—Rev. A to Rev. B
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AD9613 Data Sheet TABLE OF CONTENTS
Features .. 1 Analog Input Considerations ... 23 Applications ... 1 Voltage Reference ... 25 General Description ... 1 Clock Input Considerations .. 25 Functional Block Diagram .. 1 Power Dissipation and Standby Mode .. 27 Product Highlights ... 1 Digital Outputs ... 27 Revision History ... 2 ADC Overrange (OR) .. 27 Specifications ... 3 Channel/Chip Synchronization .. 28 ADC DC Specifications ... 3 Serial Port Interface (SPI) .. 29 ADC AC Specifications ... 4 Configuration Using the SPI ... 29 Digital Specifications ... 6 Hardware Interface ... 29 Switching Specifications .. 8 SPI Accessible Features .. 30 Timing Specifications .. 9 Memory Map .. 31 Absolute Maximum Ratings .. 11 Reading the Memory Map Register Table ... 31 Thermal Characteristics .. 11 Memory Map Register Table ... 32 ESD Caution .. 11 Memory Map Register Description ... 34 Pin Configurations and Function Descriptions ... 12 Applications Information .. 35 Typical Performance Characteristics ... 16 Design Guidelines .. 35 Equivalent Circuits ... 22 Outline Dimensions ... 36 Theory of Operation .. 23 Ordering Guide .. 36 ADC Architecture .. 23
REVISION HISTORY
Changes to Output Enable Bar and Power-Down Pin Type
2/2017—Rev. C to Rev. D
and Pin 47 Description .. 13 Changes to Table 9 .. 14 Changes to Figure 5 and Pin 7 and Pin 8 Descriptions ... 14 Changes to Pin 42 and Pin 43, Output Enable Bar and Power-
1/2013—Rev. B to Rev. C
Down Pin Type, and Pin 47 Descriptions ... 15 Changes to Features .. 1 Changes to Typical Performance Characteristics Conditions .. 16 Changes to Table 1 .. 3 Changes to Fiugre 43 .. 22 Changes to Table 2 ... 5 Added ADC Overrange (OR) Section ... 27 Change to Logic Inputs (SDIO) Paramter, Table 3... 6 Changes to Channel/Chip Synchronization Section ... 28 Changes to Table 4 .. 8 Changes to Reading the Memory Map Register Table Change to Reading the Memory Map Register Table Section ... 31 Section and Transfer Register Map Section .. 31 Changes to Table 14 .. 33 Changes to Register 0x02, Bits[5:4].. 32 Change to Memory Map Register Description Section... 34 Changes to Register 0x16, Bit 5 .. 33 Updated Outline Dimensions ... 36 Added Register 0x3A ... 34 Deleted Register 0x59 .. 34 9
/2011—Rev. A to Rev. B
Changes to Bit 0—Master Sync Buffer Enable Section ... 34 Changes to Figure 1 .. 1 Deleted SYNC Pin Control (Register 0x59) Section .. 34 Changes to Temperature Drift Parameters ... 3 Changes Output Offset Voltage (V
5/2011—Rev. 0 to Rev. A
OS), ANSI Mode Typ Parameter and Output Offset Voltage (V Changes to Table 2, AD9613-170: Worst Second or Third OS), Reduced Swing Mode Parameter.. 7 Harmonic and Worst Other (Harmonic or Spur) Max Values Changes DCO to Data Skew (t and Spurious Free Dynamic Range Min Value ... 4 SKEW) Parameters .. 8
4/2011—Revision 0: Initial Version
Rev. D | Page 2 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) ADC OVERRANGE (OR) CHANNEL/CHIP SYNCHRONIZATION SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTION Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Buffer Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE
AD9613 Data Sheet TABLE OF CONTENTS
Features .. 1 Analog Input Considerations ... 23 Applications ... 1 Voltage Reference ... 25 General Description ... 1 Clock Input Considerations .. 25 Functional Block Diagram .. 1 Power Dissipation and Standby Mode .. 27 Product Highlights ... 1 Digital Outputs ... 27 Revision History ... 2 ADC Overrange (OR) .. 27 Specifications ... 3 Channel/Chip Synchronization .. 28 ADC DC Specifications ... 3 Serial Port Interface (SPI) .. 29 ADC AC Specifications ... 4 Configuration Using the SPI ... 29 Digital Specifications ... 6 Hardware Interface ... 29 Switching Specifications .. 8 SPI Accessible Features .. 30 Timing Specifications .. 9 Memory Map .. 31 Absolute Maximum Ratings .. 11 Reading the Memory Map Register Table ... 31 Thermal Characteristics .. 11 Memory Map Register Table ... 32 ESD Caution .. 11 Memory Map Register Description ... 34 Pin Configurations and Function Descriptions ... 12 Applications Information .. 35 Typical Performance Characteristics ... 16 Design Guidelines .. 35 Equivalent Circuits ... 22 Outline Dimensions ... 36 Theory of Operation .. 23 Ordering Guide .. 36 ADC Architecture .. 23
REVISION HISTORY
Changes to Output Enable Bar and Power-Down Pin Type
2/2017—Rev. C to Rev. D
and Pin 47 Description .. 13 Changes to Table 9 .. 14 Changes to Figure 5 and Pin 7 and Pin 8 Descriptions ... 14 Changes to Pin 42 and Pin 43, Output Enable Bar and Power-
1/2013—Rev. B to Rev. C
Down Pin Type, and Pin 47 Descriptions ... 15 Changes to Features .. 1 Changes to Typical Performance Characteristics Conditions .. 16 Changes to Table 1 .. 3 Changes to Fiugre 43 .. 22 Changes to Table 2 ... 5 Added ADC Overrange (OR) Section ... 27 Change to Logic Inputs (SDIO) Paramter, Table 3... 6 Changes to Channel/Chip Synchronization Section ... 28 Changes to Table 4 .. 8 Changes to Reading the Memory Map Register Table Change to Reading the Memory Map Register Table Section ... 31 Section and Transfer Register Map Section .. 31 Changes to Table 14 .. 33 Changes to Register 0x02, Bits[5:4].. 32 Change to Memory Map Register Description Section... 34 Changes to Register 0x16, Bit 5 .. 33 Updated Outline Dimensions ... 36 Added Register 0x3A ... 34 Deleted Register 0x59 .. 34 9
/2011—Rev. A to Rev. B
Changes to Bit 0—Master Sync Buffer Enable Section ... 34 Changes to Figure 1 .. 1 Deleted SYNC Pin Control (Register 0x59) Section .. 34 Changes to Temperature Drift Parameters ... 3 Changes Output Offset Voltage (V
5/2011—Rev. 0 to Rev. A
OS), ANSI Mode Typ Parameter and Output Offset Voltage (V Changes to Table 2, AD9613-170: Worst Second or Third OS), Reduced Swing Mode Parameter.. 7 Harmonic and Worst Other (Harmonic or Spur) Max Values Changes DCO to Data Skew (t and Spurious Free Dynamic Range Min Value ... 4 SKEW) Parameters .. 8
4/2011—Revision 0: Initial Version
Rev. D | Page 2 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) ADC OVERRANGE (OR) CHANNEL/CHIP SYNCHRONIZATION SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTION Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Buffer Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations VCM SPI Port OUTLINE DIMENSIONS ORDERING GUIDE
