Datasheet AD7606, AD7606-6, AD7606-4 (Analog Devices) - 9

Data Sheet AD7606/AD7606-6/AD7606-4 Limit at TMIN, TMAX Limit at TMIN, TMAX (0.1 × VDRIVE and (0.3 × VDRIVE and 0.9 × VDRIVE 0.7 × VDRIVE Logic Input Levels) Logic Input Levels) Parameter Min Typ Max Min Typ Max Unit Description
t27 Delay from RD falling edge to FRSTDATA low 19 22 ns VDRIVE = 3.3 V to 5.25V 24 29 ns VDRIVE = 2.3 V to 2.7V t28 Delay from 16th SCLK falling edge to FRSTDATA low 17 20 ns VDRIVE = 3.3 V to 5.25V 22 27 ns VDRIVE = 2.3 V to 2.7V t29 24 29 ns Delay from CS rising edge until FRSTDATA three- state enabled 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. 2 In oversampling mode, typical tCONV for the AD7606-6 and AD7606-4 can be calculated using ((N × tCONV) + ((N − 1) × 1 µs)). N is the oversampling ratio. For the AD7606-6, tCONV = 3 µs; and for the AD7606-4, tCONV = 2 µs. 3 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <10 LSB performance matching between channel sets. 4 A buffer is used on the data output pins for these measurements, which is equivalent to a load of 20 pF on the output pins.
Timing Diagrams t5 CONVST A, CONVST B tCYCLE t2 CONVST A, CONVST B t3 tCONV t1 BUSY t4 CS t7 tRESET RESET
002 08479- Figure 2. CONVST Timing—Reading After a Conversion
t5 CONVST A, CONVST B tCYCLE t2 CONVST A, CONVST B t3 tCONV t1 BUSY t6 CS t7 tRESET RESET
003 08479- Figure 3. CONVST Timing—Reading During a Conversion Rev. C | Page 9 of 36 Document Outline Features Applications Functional Block Diagram Revision History General Description Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Converter Details Analog Input Analog Input Ranges Analog Input Impedance Analog Input Clamp Protection Analog Input Antialiasing Filter Track-and-Hold Amplifiers ADC Transfer Function Internal/External Reference Typical Connection Diagram Power-Down Modes Conversion Control Simultaneous Sampling on All Analog Input Channels Simultaneously Sampling Two Sets of Channels Digital Interface Parallel Interface (PAR/SER/BYTE SEL = 0) Parallel Byte (PAR/SER/BYTE SEL = 1, DB15 = 1) Serial Interface (PAR/SER/BYTE SEL = 1) Reading During Conversion Digital Filter Layout Guidelines Outline Dimensions Ordering Guide