Datasheet AD7195 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA and AC Excitation |
| Pages / Page | 45 / 4 — Data Sheet. AD7195. SPECIFICATIONS. Table 1. Parameter. Min. Typ. Max. … |
| Revision | A |
| File Format / Size | PDF / 1.0 Mb |
| Document Language | English |
Data Sheet. AD7195. SPECIFICATIONS. Table 1. Parameter. Min. Typ. Max. Unit. Test Conditions/Comments1
Model Line for this Datasheet
Text Version of Document
link to page 6 link to page 14 link to page 14 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6 link to page 6
Data Sheet AD7195 SPECIFICATIONS
AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFIN(+) = AVDD, REFIN(−) = AGND, MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments1
ADC Output Data Rate 4.7 4800 Hz Chop disabled 1.17 1200 Hz Chop enabled, sinc4 filter 1.56 1600 Hz Chop enabled, sinc3 filter No Missing Codes2 24 Bits FS > 1, sinc4 filter3 24 Bits FS > 4, sinc3 filter3 Resolution See the RMS Noise and Resolution section RMS Noise and Output See the RMS Noise and Resolution section Data Rates Integral Nonlinearity Gain = 12 ±1 ±5 ppm of FSR Gain > 1 ±5 ±15 ppm of FSR Offset Error4, 5 ±75/gain µV Chop disabled ±0.5 µV Chop enabled Offset Error Drift vs. ±100/gain nV/°C Gain = 1 to 16; chop disabled Temperature ±5 nV/°C Gain = 32 to 128; chop disabled ±5 nV/°C Chop enabled Offset Error Drift vs. Time 25 nV/1000 Gain > 32 hours Gain Error4 ±0.001 ±0.005 % max AVDD = 5 V, gain = 1, TA = 25°C (factory calibration conditions) ±0.006 % Gain > 1, post internal full-scale calibration Gain Drift vs. Temperature ±1 ppm/°C Gain Drift vs. Time 10 ppm/1000 Gain = 1 hours Power Supply Rejection 95 dB Gain = 1, VIN = 1 V 98 103 Gain = 8, VIN = 1 V/gain 100 110 dB Gain > 8, VIN = 1 V/gain Common-Mode Rejection @ DC2 100 115 dB min Gain = 1, VIN = 1 V @ DC 115 140 dB min Gain > 1, VIN = 1 V/gain @ 50 Hz, 60 Hz2 120 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz @ 50 Hz, 60 Hz2 120 dB 50 ± 1 Hz (50 Hz output data rate), 60 ± 1 Hz (60 Hz output data rate) Normal Mode Rejection2 Sinc4 Filter Internal Clock @ 50 Hz, 60 Hz 100 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 74 dB 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz @ 50 Hz 96 dB 50 Hz output data rate, 50 ± 1 Hz @ 60 Hz 97 dB 60 Hz output data rate, 60 ± 1 Hz External Clock @ 50 Hz, 60 Hz 120 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 82 dB 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz @ 50 Hz 120 dB 50 Hz output data rate, 50 ± 1 Hz @ 60 Hz 120 dB 60 Hz output data rate, 60 ± 1 Hz Sinc3 Filter Internal Clock @ 50 Hz, 60 Hz 75 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 60 dB 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz @ 50 Hz 70 dB 50 Hz output data rate, 50 ± 1 Hz @ 60 Hz 70 dB 60 Hz output data rate, 60 ± 1 Hz Rev. A | Page 3 of 44 Document Outline FEATURES INTERFACE APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Circuit and Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED SINC4 CHOP ENABLED SINC3 CHOP ENABLED ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER MODE REGISTER CONFIGURATION REGISTER DATA REGISTER ID REGISTER GPOCON REGISTER OFFSET REGISTER FULL-SCALE REGISTER ADC CIRCUIT INFORMATION OVERVIEW Analog Inputs Multiplexer PGA Reference Detect Burnout Currents Σ-Δ ADC and Filter AC Excitation Serial Interface Clock Temperature Sensor Calibration ANALOG INPUT CHANNEL PGA REFERENCE REFERENCE DETECT BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING BURNOUT CURRENTS AC EXCITATION CHANNEL SEQUENCER Single Conversion Mode Continuous Conversion Mode Continuous Read RESET SYSTEM SYNCHRONIZATION CLOCK ENABLE PARITY TEMPERATURE SENSOR BRIDGE POWER-DOWN SWITCH CALIBRATION DIGITAL FILTER SINC4 FILTER (CHOP DISABLED) Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sinc4 50 Hz/60 Hz Rejection SINC3 FILTER (CHOP DISABLED) Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sinc3 50 Hz/60 Hz Rejection CHOP ENABLED (SINC4 FILTER) Output Data Rate and Settling Time (Sinc4 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc4 Chop Enabled) CHOP ENABLED (SINC3 FILTER) Output Data Rate and Settling Time (Sinc3 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc3 Chop Enabled) SUMMARY OF FILTER OPTIONS GROUNDING AND LAYOUT APPLICATIONS INFORMATION WEIGH SCALES OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7195 SPECIFICATIONS
AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFIN(+) = AVDD, REFIN(−) = AGND, MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments1
ADC Output Data Rate 4.7 4800 Hz Chop disabled 1.17 1200 Hz Chop enabled, sinc4 filter 1.56 1600 Hz Chop enabled, sinc3 filter No Missing Codes2 24 Bits FS > 1, sinc4 filter3 24 Bits FS > 4, sinc3 filter3 Resolution See the RMS Noise and Resolution section RMS Noise and Output See the RMS Noise and Resolution section Data Rates Integral Nonlinearity Gain = 12 ±1 ±5 ppm of FSR Gain > 1 ±5 ±15 ppm of FSR Offset Error4, 5 ±75/gain µV Chop disabled ±0.5 µV Chop enabled Offset Error Drift vs. ±100/gain nV/°C Gain = 1 to 16; chop disabled Temperature ±5 nV/°C Gain = 32 to 128; chop disabled ±5 nV/°C Chop enabled Offset Error Drift vs. Time 25 nV/1000 Gain > 32 hours Gain Error4 ±0.001 ±0.005 % max AVDD = 5 V, gain = 1, TA = 25°C (factory calibration conditions) ±0.006 % Gain > 1, post internal full-scale calibration Gain Drift vs. Temperature ±1 ppm/°C Gain Drift vs. Time 10 ppm/1000 Gain = 1 hours Power Supply Rejection 95 dB Gain = 1, VIN = 1 V 98 103 Gain = 8, VIN = 1 V/gain 100 110 dB Gain > 8, VIN = 1 V/gain Common-Mode Rejection @ DC2 100 115 dB min Gain = 1, VIN = 1 V @ DC 115 140 dB min Gain > 1, VIN = 1 V/gain @ 50 Hz, 60 Hz2 120 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz @ 50 Hz, 60 Hz2 120 dB 50 ± 1 Hz (50 Hz output data rate), 60 ± 1 Hz (60 Hz output data rate) Normal Mode Rejection2 Sinc4 Filter Internal Clock @ 50 Hz, 60 Hz 100 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 74 dB 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz @ 50 Hz 96 dB 50 Hz output data rate, 50 ± 1 Hz @ 60 Hz 97 dB 60 Hz output data rate, 60 ± 1 Hz External Clock @ 50 Hz, 60 Hz 120 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 82 dB 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz @ 50 Hz 120 dB 50 Hz output data rate, 50 ± 1 Hz @ 60 Hz 120 dB 60 Hz output data rate, 60 ± 1 Hz Sinc3 Filter Internal Clock @ 50 Hz, 60 Hz 75 dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 60 dB 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz @ 50 Hz 70 dB 50 Hz output data rate, 50 ± 1 Hz @ 60 Hz 70 dB 60 Hz output data rate, 60 ± 1 Hz Rev. A | Page 3 of 44 Document Outline FEATURES INTERFACE APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Circuit and Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED SINC4 CHOP ENABLED SINC3 CHOP ENABLED ON-CHIP REGISTERS COMMUNICATIONS REGISTER STATUS REGISTER MODE REGISTER CONFIGURATION REGISTER DATA REGISTER ID REGISTER GPOCON REGISTER OFFSET REGISTER FULL-SCALE REGISTER ADC CIRCUIT INFORMATION OVERVIEW Analog Inputs Multiplexer PGA Reference Detect Burnout Currents Σ-Δ ADC and Filter AC Excitation Serial Interface Clock Temperature Sensor Calibration ANALOG INPUT CHANNEL PGA REFERENCE REFERENCE DETECT BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING BURNOUT CURRENTS AC EXCITATION CHANNEL SEQUENCER Single Conversion Mode Continuous Conversion Mode Continuous Read RESET SYSTEM SYNCHRONIZATION CLOCK ENABLE PARITY TEMPERATURE SENSOR BRIDGE POWER-DOWN SWITCH CALIBRATION DIGITAL FILTER SINC4 FILTER (CHOP DISABLED) Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sinc4 50 Hz/60 Hz Rejection SINC3 FILTER (CHOP DISABLED) Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sinc3 50 Hz/60 Hz Rejection CHOP ENABLED (SINC4 FILTER) Output Data Rate and Settling Time (Sinc4 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc4 Chop Enabled) CHOP ENABLED (SINC3 FILTER) Output Data Rate and Settling Time (Sinc3 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc3 Chop Enabled) SUMMARY OF FILTER OPTIONS GROUNDING AND LAYOUT APPLICATIONS INFORMATION WEIGH SCALES OUTLINE DIMENSIONS ORDERING GUIDE
