Datasheet AD7985 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 16-Bit, 2.5 MSPS PulSAR 11 mW ADC in QFN |
| Pages / Page | 29 / 9 — AD7985. Data Sheet. Pin No. Mnemonic. Type1 Description |
| Revision | C |
| File Format / Size | PDF / 650 Kb |
| Document Language | English |
AD7985. Data Sheet. Pin No. Mnemonic. Type1 Description
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AD7985 Data Sheet Pin No. Mnemonic Type1 Description
19 BVDD P Reference Buffer Power. Nominally at 5.0 V. If an external reference buffer is used to achieve the maximum SNR performance with a 5 V reference, the reference buffer must be powered down by connecting the REFIN pin to ground. The external reference buffer must be connected to the BVDD pin. 20 REFIN AI/O Internal Reference Output/Reference Buffer Input. When PDREF is low, the internal band gap reference produces a 1.2 V (typical) voltage on this pin, which needs external decoupling (0.1 µF typical). When PDREF is high, use an external reference to provide 1.2 V (typical) to this pin. When PDREF is high and REFIN is low, the on-chip reference buffer and the band gap reference are powered down. An external reference must be connected to REF and BVDD. 21 Exposed Pad EP The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane. 1 AI = analog input, AI/O = bidirectional analog, DI = digital input, DO = digital output, and P = power. Rev. C | Page 8 of 28 Document Outline FEATURES APPLICATIONS APPLICATION DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION CONVERSION MODES OF OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM ANALOG INPUTS DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT Internal Reference, REF = 4.096 V (PDREF Low) External 1.2 V Reference and Internal Buffer (PDREF High) External Reference (PDREF High, REFIN Low) Reference Decoupling POWER SUPPLY DIGITAL INTERFACE DATA READING OPTIONS Reading During Conversion, Fast Host (Turbo or Normal Mode) Split-Reading, Any Speed Host (Turbo or Normal Mode) Reading During Acquisition, Any Speed Host (Turbo or Normal Mode) /CS MODE, 3-WIRE WITHOUT BUSY INDICATOR /CS MODE, 3-WIRE WITH BUSY INDICATOR /CS MODE, 4-WIRE WITHOUT BUSY INDICATOR /CS MODE, 4-WIRE WITH BUSY INDICATOR CHAIN MODE WITHOUT BUSY INDICATOR CHAIN MODE WITH BUSY INDICATOR APPLICATIONS INFORMATION LAYOUT EVALUATING THE AD7985 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
19 BVDD P Reference Buffer Power. Nominally at 5.0 V. If an external reference buffer is used to achieve the maximum SNR performance with a 5 V reference, the reference buffer must be powered down by connecting the REFIN pin to ground. The external reference buffer must be connected to the BVDD pin. 20 REFIN AI/O Internal Reference Output/Reference Buffer Input. When PDREF is low, the internal band gap reference produces a 1.2 V (typical) voltage on this pin, which needs external decoupling (0.1 µF typical). When PDREF is high, use an external reference to provide 1.2 V (typical) to this pin. When PDREF is high and REFIN is low, the on-chip reference buffer and the band gap reference are powered down. An external reference must be connected to REF and BVDD. 21 Exposed Pad EP The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane. 1 AI = analog input, AI/O = bidirectional analog, DI = digital input, DO = digital output, and P = power. Rev. C | Page 8 of 28 Document Outline FEATURES APPLICATIONS APPLICATION DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION CONVERSION MODES OF OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM ANALOG INPUTS DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT Internal Reference, REF = 4.096 V (PDREF Low) External 1.2 V Reference and Internal Buffer (PDREF High) External Reference (PDREF High, REFIN Low) Reference Decoupling POWER SUPPLY DIGITAL INTERFACE DATA READING OPTIONS Reading During Conversion, Fast Host (Turbo or Normal Mode) Split-Reading, Any Speed Host (Turbo or Normal Mode) Reading During Acquisition, Any Speed Host (Turbo or Normal Mode) /CS MODE, 3-WIRE WITHOUT BUSY INDICATOR /CS MODE, 3-WIRE WITH BUSY INDICATOR /CS MODE, 4-WIRE WITHOUT BUSY INDICATOR /CS MODE, 4-WIRE WITH BUSY INDICATOR CHAIN MODE WITHOUT BUSY INDICATOR CHAIN MODE WITH BUSY INDICATOR APPLICATIONS INFORMATION LAYOUT EVALUATING THE AD7985 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
