Datasheet AD7626 (Analog Devices) - 10

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Data Sheet AD7626 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 2 2 2 F F F ND ND RE G RE RE CAP G CAP CAP 32 31 30 29 28 27 26 25 VDD1 1 24 GND VDD2 2 23 IN+ CAP1 3 22 IN– AD7626 REFIN 4 21 VCM TOP VIEW EN0 5 20 VDD1 (Not to Scale) EN1 6 19 VDD1 VDD2 7 18 VDD2 CNV– 8 17 CLK+ 9 10 11 12 13 14 15 16 + O – + D– D+ VI ND K– G CNV DCO DCO CL NOTES
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1. CONNECT THE EXPOSED PAD TO THE GROUND PLANE OF THE PCB USING MULTIPLE VIAS.
07648- Figure 4. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1 VDD1 P Analog 5 V Supply. Decouple the 5 V supply with a 100 nF capacitor. 2 VDD2 P Analog 2.5 V Supply. Decouple this pin with a 100 nF capacitor. The 2.5 V supply source should supply this pin first, then be traced to the other VDD2 pins (Pin 7 and Pin 18). 3 CAP1 AO Connect this pin to a 10 nF capacitor. 4 REFIN AI/O Prebuffer Reference Voltage. When using the internal reference, this pin outputs the band gap voltage and is nominally at 1.2 V. It can be overdriven with an external reference voltage such as the ADR280. In either internal or external reference mode, a 10 μF capacitor is required. If using an external 4.096 V reference (connected to REF), this pin is a no connect and does not require any capacitor. 5, 6 EN0, EN1 DI Enable. Operates from 2.5 V logic. The logic levels of these pins set the operation of the device as fol ows: EN1 = 0, EN0 = 0: power-down mode. EN1 = 0, EN0 = 1: external 1.2 V reference applied to the REFIN pin required. EN1 = 1, EN0 = 0: external 4.096 V reference applied to the REF pin required. EN1 = 1, EN0 = 1: internal reference and internal reference buffer in use. 7 VDD2 P Digital 2.5 V Supply. Decouple this pin with a 100 nF capacitor. 8, 9 CNV−, CNV+ DI Convert Input. These pins act as the conversion control pin. On the rising edge of these pins, the analog inputs are sampled and a conversion cycle is initiated. CNV+ works as a CMOS input when CNV− is grounded; otherwise, CNV+ and CNV− are differential LVDS inputs. 10, 11 D−, D+ DO LVDS Data Outputs. The conversion data is output serially on these pins. 12 VIO P Input/Output Interface Supply. Use a 2.5 V supply and decouple this pin with a 100 nF capacitor. 13 GND P Ground. Return path for the 100 nF capacitor connected to Pin 12. 14, 15 DCO−, DCO+ DO LVDS Buffered Clock Outputs. When DCO+ is grounded, the self clocked interface mode is selected. In this mode, the 16-bit results on D are preceded by an initial 0 (which is output at the end of the previous conversion), followed by a 2-bit header (10) to allow synchronization of the data by the digital host with extra logic. The 1 in this header provides the reference to acquire the subsequent conversion result correctly. When DCO+ is not grounded, the echoed clock interface mode is selected. In this mode, DCO± is a copy of CLK±. The data bits are output on the falling edge of DCO+ and can be captured in the digital host on the next rising edge of DCO+. 16, 17 CLK−, CLK+ DI LVDS Clock Inputs. This clock shifts out the conversion results on the falling edge of CLK+. 18 VDD2 P Analog 2.5 V Supply. Decouple this pin with a 100 nF capacitor. 19, 20 VDD1 P Analog 5 V Supply. Isolate these pins from Pin 1 with a ferrite bead and decouple them with a 100 nF capacitor. 21 VCM AO Common-Mode Output. When using any reference scheme, this pin produces one half the voltage present on the REF pin, which can be useful for driving the common mode of the input amplifiers. 22 IN− AI Differential Negative Analog Input. Referenced to and must be driven 180° out of phase with IN+. 23 IN+ AI Differential Positive Analog Input. Referenced to and must be driven 180° out of phase with IN−. 24 GND P Ground. Rev. D | Page 9 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER INFORMATION TRANSFER FUNCTIONS ANALOG INPUTS TYPICAL CONNECTION DIAGRAM DRIVING THE AD7626 Differential Analog Input Source Single-Ended to Differential Driver Single-Ended or Fully Differential High Frequency Driver VOLTAGE REFERENCE OPTIONS Wake-Up Time from EN1 = 0, EN0 = 0 POWER SUPPLY Power-Up DIGITAL INTERFACE Conversion Control Echoed Clock Interface Mode Self Clocked Mode APPLICATIONS INFORMATION LAYOUT, DECOUPLING, AND GROUNDING Exposed Paddle VDD1 Supply Routing and Decoupling VIO Supply Decoupling Layout and Decoupling of Pin 25 to Pin 32 OUTLINE DIMENSIONS ORDERING GUIDE