Datasheet AD7170 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 12-Bit Low Power Σ−Δ ADC |
| Pages / Page | 15 / 6 — Data Sheet. AD7170. TIMING CHARACTERISTICS. Table 2. Parameter1, 2. Limit … |
| Revision | B |
| File Format / Size | PDF / 373 Kb |
| Document Language | English |
Data Sheet. AD7170. TIMING CHARACTERISTICS. Table 2. Parameter1, 2. Limit at TMIN, TMAX. Unit. Conditions/Comments
Model Line for this Datasheet
Text Version of Document
link to page 6 link to page 6
Data Sheet AD7170 TIMING CHARACTERISTICS
VDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = VDD, unless otherwise noted.
Table 2. Parameter1, 2 Limit at TMIN, TMAX Unit Conditions/Comments
READ t1 100 ns min SCLK high pulse width t2 100 ns min SCLK low pulse width t 3 3 0 ns min SCLK active edge to data valid delay4 60 ns max VDD = 4.75 V to 5.25 V 80 ns max VDD = 2.7 V to 3.6 V t4 10 ns min SCLK inactive edge to DOUT/RDY high RESET t5 100 ns min PDRST low pulse width t6 25 ms typ PDRST high to data valid delay 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 See Figure 3. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 SCLK active edge is the falling edge of SCLK.
ISINK (1.6mA WITH VDD = 5V, 100µA WITH VDD = 3V) TO OUTPUT 1.6V PIN 50pF I
002
SOURCE (200µA WITH VDD = 5V, 100µA WITH VDD = 3V)
08416- Figure 2. Load Circuit for Timing Characterization
TIMING DIAGRAMS DOUT/RDY (O) MSB LSB t t4 3 t1 SCLK (I) t2
003
I = INPUT, O = OUTPUT
08416- Figure 3. Read Cycle Timing Diagram
PDRST (I) t5 t6 DOUT/RDY (O)
004
I = INPUT, O = OUTPUT
08416- Figure 4. Resetting the AD7170 Rev. B | Page 5 of 14 Document Outline FEATURES INTERFACE APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE AND RESOLUTION SPECIFICATIONS ADC CIRCUIT INFORMATION OVERVIEW FILTER, DATA RATE, AND SETTLING TIME GAIN POWER-DOWN/RESET (PDRST\) ANALOG INPUT CHANNEL BIPOLAR CONFIGURATION DATA OUTPUT CODING REFERENCE DIGITAL INTERFACE GROUNDING AND LAYOUT APPLICATIONS INFORMATION TEMPERATURE SYSTEM SIGNAL CONDITIONING CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7170 TIMING CHARACTERISTICS
VDD = 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = VDD, unless otherwise noted.
Table 2. Parameter1, 2 Limit at TMIN, TMAX Unit Conditions/Comments
READ t1 100 ns min SCLK high pulse width t2 100 ns min SCLK low pulse width t 3 3 0 ns min SCLK active edge to data valid delay4 60 ns max VDD = 4.75 V to 5.25 V 80 ns max VDD = 2.7 V to 3.6 V t4 10 ns min SCLK inactive edge to DOUT/RDY high RESET t5 100 ns min PDRST low pulse width t6 25 ms typ PDRST high to data valid delay 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2 See Figure 3. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 SCLK active edge is the falling edge of SCLK.
ISINK (1.6mA WITH VDD = 5V, 100µA WITH VDD = 3V) TO OUTPUT 1.6V PIN 50pF I
002
SOURCE (200µA WITH VDD = 5V, 100µA WITH VDD = 3V)
08416- Figure 2. Load Circuit for Timing Characterization
TIMING DIAGRAMS DOUT/RDY (O) MSB LSB t t4 3 t1 SCLK (I) t2
003
I = INPUT, O = OUTPUT
08416- Figure 3. Read Cycle Timing Diagram
PDRST (I) t5 t6 DOUT/RDY (O)
004
I = INPUT, O = OUTPUT
08416- Figure 4. Resetting the AD7170 Rev. B | Page 5 of 14 Document Outline FEATURES INTERFACE APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTPUT NOISE AND RESOLUTION SPECIFICATIONS ADC CIRCUIT INFORMATION OVERVIEW FILTER, DATA RATE, AND SETTLING TIME GAIN POWER-DOWN/RESET (PDRST\) ANALOG INPUT CHANNEL BIPOLAR CONFIGURATION DATA OUTPUT CODING REFERENCE DIGITAL INTERFACE GROUNDING AND LAYOUT APPLICATIONS INFORMATION TEMPERATURE SYSTEM SIGNAL CONDITIONING CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE
