Datasheet AD9251 (Analog Devices) - 6

Data Sheet AD9251 AC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS disabled, unless otherwise noted.
Table 2. AD9251-20/AD9251-40 AD9251-65 AD9251-80 Parameter1 Temp Min Typ Max Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz 25°C 74.7 74.5 74.3 dBFS fIN = 30.5 MHz 25°C 74.4 74.3 74.1 dBFS Full 73.6 73.6 dBFS fIN = 70 MHz 25°C 73.7 73.7 73.6 dBFS Full 72.5 dBFS fIN = 200 MHz 25°C 71.5 71.5 71.5 dBFS SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 9.7 MHz 25°C 74.6 74.4 74.1 dBFS fIN = 30.5 MHz 25°C 74.3 74.2 74.0 dBFS Full 73.4 73.4 dBFS fIN = 70 MHz 25°C 73.6 73.6 73.5 dBFS Full 72.4 dBFS fIN = 200 MHz 25°C 70.0 70.0 70.0 dBFS EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz 25°C 12.0 12.0 12.0 Bits fIN = 30.5 MHz 25°C 12.0 12.0 12.0 Bits fIN = 70 MHz 25°C 11.9 11.9 11.9 Bits fIN = 200 MHz 25°C 11.3 11.3 11.3 Bits WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz 25°C −95 −95 −93 dBc fIN = 30.5 MHz 25°C −95 −95 −93 dBc Full −81 −81 dBc fIN = 70 MHz 25°C −94 −94 −92 dBc Full −81 dBc fIN = 200 MHz 25°C −80 −80 −80 dBc SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz 25°C 95 95 93 dBc fIN = 30.5 MHz 25°C 94 94 93 dBc Full 81 81 dBc fIN = 70 MHz 25°C 93 93 92 dBc Full 81 dBc fIN = 200 MHz 25°C 80 80 80 dBc WORST OTHER (HARMONIC OR SPUR) fIN = 9.7 MHz 25°C −98 −98 −97 dBc fIN = 30.5 MHz 25°C −98 −98 −97 dBc Full −90 −90 dBc fIN = 70 MHz 25°C −98 −98 −96 dBc Full −89 dBc fIN = 200 MHz 25°C −95 −95 −95 dBc TWO-TONE SFDR fIN = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS) 25°C 90 90 90 dBc CROSSTALK2 Full −110 −110 −110 dBc ANALOG INPUT BANDWIDTH 25°C 700 700 700 MHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel. Rev. B | Page 5 of 36 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9251-80 AD9251-65 AD9251-40 AD9251-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable Bit 7—Enable OEB Pin 47 Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE