Datasheet AD9268 (Analog Devices) - 20

AD9268 0 0 105MSPS 105MSPS 2.4MHz @ –6dBFS 200.3MHz @ –1dBFS –20 SNR = 78.2dB (79.2dBFS) –20 SNR = 74.0dB (75.0dBFS) SFDR = 90dBc SFDR = 79dBc –40 –40 ) ) S S BF SECOND HARMONIC BF SECOND THIRD HARMONIC d –60 d HARMONIC ( –60 ( THIRD HARMONIC UDE UDE IT –80 IT L –80 L P P AM AM –100 –100 –120 –120 –140 –140
74 77 0
0 10 20 30 40 50
0
0 10 20 30 40 50
3- 3-
FREQUENCY (MHz)
12
FREQUENCY (MHz)
12 08 08 Figure 20. AD9268-105 Single-Tone FFT with fIN = 2.4 MHz Figure 23. AD9268-105 Single-Tone FFT with fIN = 200.3 MHz
0 0 105MSPS 105MSPS 70.1MHz @ –1dBFS 70.1MHz @ –6dBFS –20 SNR = 77.5dB (78.5dBFS) –20 SNR = 72.7dB (78.7dBFS) SFDR = 93.0dBc SFDR = 97.6dBc –40 –40 ) ) S S BF BF d –60 d ( –60 SECOND ( SECOND THIRD HARMONIC HARMONIC THIRD HARMONIC HARMONIC UDE UDE IT –80 IT L –80 L P P AM AM –100 –100 –120 –120 –140 –140
75 78 0
0 10 20 30 40 50
0 3-
0 10 20 30 40 50
3-
FREQUENCY (MHz)
12
FREQUENCY (MHz)
12 08 08 Figure 21. AD9268-105 Single-Tone FFT with fIN = 70.1 MHz Figure 24. AD9268-105 Single-Tone FFT with fIN = 70.1 MHz with Dither Enabled
0 120 105MSPS 140.1MHz @ –1dBFS –20 SNR = 75.7dB (76.7dBFS) 100 SFDR = 85.5dBc ) S –40 ) BF S 80 SECOND HARMONIC BF d ND d –60 ( A THIRD HARMONIC 60 Bc UDE d IT –80 L P DR ( F S 40 AM –100 NR/ S SNR (dBFS) 20 –120 SFDR (dBc) SNR (dBc) SFDR (dBFS) –140 0
76 79 0
0 10 20 30 40 50 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0
0 3- 3- 12
FREQUENCY (MHz)
12
INPUT AMPLITUDE (dBFS)
08 08 Figure 22. AD9268-105 Single-Tone FFT with fIN = 140.1 MHz Figure 25. AD9268-105 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 98.12 MHz Rev. A | Page 19 of 44 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Common-Mode Voltage Servo Dither Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE