Datasheet AD9268 (Analog Devices) - 31

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AD9268 External Reference Operation
The RF balun configuration is recommended for clock frequencies The use of an external reference may be necessary to enhance between 125 MHz and 625 MHz, and the RF transformer is recom- the gain accuracy of the ADC or improve thermal drift charac- mended for clock frequencies from 10 MHz to 200 MHz. The teristics. Figure 73 shows the typical drift characteristics of the back-to-back Schottky diodes across the transformer/balun internal reference in 1.0 V mode. secondary limit clock excursions into the AD9268 to approx- imately 0.8 V p-p differential. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal This limit helps prevent the large voltage swings of the clock reference buffer loads the external reference with an equivalent from feeding through to other portions of the AD9268 while 6 kΩ load (see Figure 62). The internal buffer generates the positive preserving the fast rise and fall times of the signal that are critical and negative full-scale references for the ADC core. Therefore, to a low jitter performance. the external reference must be limited to a maximum of 1.0 V.
Mini-Circuits® ADC 2.0 ADT1-1WT, 1:1Z AD9268 0.1µF 0.1µF XFMR 1.5 CLOCK ) CLK+ V INPUT m VREF = 1.0V 50Ω 100Ω R ( 1.0 0.1µF CLK– RRO 0.5 SCHOTTKY
5
E 0.1µF
4 0
E DIODES:
3-
G HSMS2822
12
A
08
T 0 L
Figure 75. Transformer-Coupled Differential Clock (Up to 200 MHz)
O V –0.5 NCE RE ADC –1.0 E F AD9268 1nF 0.1µF RE CLOCK –1.5 CLK+ INPUT 50Ω –2.0 0.1µF
55
–40 –20 0 20 40 60 80
0
1nF CLK–
3-
TEMPERATURE (°C)
12
SCHOTTKY
46 08 0
DIODES:
3- Figure 73. Typical VREF Drift
HSMS2822
812 0
CLOCK INPUT CONSIDERATIONS
Figure 76. Balun-Coupled Differential Clock (Up to 625 MHz) For optimum performance, the AD9268 sample clock inputs, If a low jitter clock source is not available, another option is to CLK+ and CLK−, should be clocked with a differential signal. ac couple a differential PECL signal to the sample clock input The signal is typically ac-coupled into the CLK+ and CLK− pins pins, as shown in Figure 77. The AD9510/AD9511/AD9512/ via a transformer or capacitors. These pins are biased internally AD9513/AD9514/AD9515/AD9516/AD9517/AD9518 clock (see Figure 74) and require no external bias. If the inputs are drivers offer excellent jitter performance. floated, the CLK− pin is pulled low to prevent spurious clocking.
AVDD 0.1µF 0.1µF CLOCK CLK+ INPUT AD951x ADC 0.9V 100Ω PECL DRIVER AD9268 0.1µF 0.1µF CLOCK CLK– CLK+ CLK– INPUT 50kΩ 50kΩ 240Ω 240Ω
47 0 123-
4pF 4pF
08 Figure 77. Differential PECL Sample Clock (Up to 625 MHz) 4 -04 23 A third option is to ac couple a differential LVDS signal to the 81 0 Figure 74. Equivalent Clock Input Circuit sample clock input pins, as shown in Figure 78. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/
Clock Input Options
AD9518 clock drivers offer excellent jitter performance. The AD9268 has a very flexible clock input structure. Clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most
0.1µF 0.1µF CLOCK CLK+
concern, as described in the Jitter Considerations section.
INPUT AD951x ADC 100Ω
Figure 75 and Figure 76 show two preferred methods for clocking
0.1µF LVDS DRIVER AD9268 0.1µF CLOCK
the AD9268 (at clock rates up to 625 MHz). A low jitter clock
CLK– INPUT 50kΩ 50kΩ
048 source is converted from a single-ended signal to a differential 08123- signal using either an RF balun or an RF transformer. Figure 78. Differential LVDS Sample Clock (Up to 625 MHz) Rev. A | Page 30 of 44 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ADC DC SPECIFICATIONS ADC AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Common-Mode Voltage Servo Dither Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations CHANNEL/CHIP SYNCHRONIZATION POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations VCM RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE