Datasheet AD7357 (Analog Devices) - 9

ManufacturerAnalog Devices
DescriptionDifferential Input, Dual, Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC
Pages / Page25 / 9 — AD7357. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. D N. …
RevisionE
File Format / SizePDF / 701 Kb
Document LanguageEnglish

AD7357. Data Sheet. PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS. D N. INB–. VINA+. INB+. 12 NIC. TOP VIEW. NIC 3. 11 VDRIVE. (Not to Scale)

AD7357 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS D N INB– VINA+ INB+ 12 NIC TOP VIEW NIC 3 11 VDRIVE (Not to Scale)

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AD7357 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS D N D B G A F N F F A E G E E NI R A R R V 8 7 6 5 4 1 1 1 1 1 V 1 13 INB– VINA+ V 2 INB+ AD7357 12 NIC TOP VIEW NIC 3 11 VDRIVE V 1 (Not to Scale) INA+ 16 VDRIVE V 4 10 DD SCLK V 2 INA– 15 SCLK REF 3 A 14 SDATAA AD7357 5 6 7 8 9 S D D B A REFGND 4 TOP VIEW 13 SDATA C A A B N N (Not to Scale) G G T T A D A A AGND 5 12 DGND D D S S REF 6 NOTES B 11 AGND 1. NIC = NO INTERNAL CONNECTION. V 7 2. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. INB– 10 CS FOR INCREASED RELIABILITY OF THE SOLDER
2
V 8 JOINTS AND FOR MAXIMUM THERMAL CAPABILITY,
03
INB+ 9 VDD
00 1 7-
SOLDER THE EXPOSED PAD TO THE PRINTED
7- 75
CIRCUIT BOARD (PCB).
75 07 07 Figure 2. Pin Configuration, TSSOP Figure 3. Pin Configuration, LFCSP
Table 5. Pin Function Descriptions Pin No. T Mn SSOP LFCSP emonic Description
1, 2 13, 14 VINA+, VINA− Analog Inputs of ADC A. These analog inputs form a fully differential pair. 3, 6 15, 18 REFA, REFB Reference Decoupling Capacitor Pins. Decoupling capacitors are connected between these pins and the REFGND pin to decouple the reference buffer for each respective ADC. It is recommended to decouple each reference pin with a 10 μF capacitor. Provided that the output is buffered, take the on-chip reference from these pins and apply it externally to the rest of the system. The nominal internal reference voltage is 2.048 V and appears at these pins. These pins can also be overdriven by an external reference. The input voltage range for the external reference is 2.048 V + 100 mV to VDD. 4 16 REFGND Reference Ground. This is the ground reference point for the reference circuitry on the AD7357. Refer any external reference signal to this REFGND voltage. Decoupling capacitors must be placed between this pin and the REFA and REFB pins. 5, 11 6, 17 AGND Analog Ground. This is the ground reference point for all analog circuitry on the AD7357. Refer all analog input signals to this AGND voltage. The AGND and DGND voltages must ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 7, 8 1, 2 VINB−, VINB+ Analog Inputs of ADC B. These analog inputs form a fully differential pair. 9 4 VDD Power Supply Input. The VDD range for the AD7357 is 2.5 V ± 10%. Decouple the supply to AGND with a 0.1 μF capacitor and a 10 μF tantalum capacitor. 10 5 CS Chip Select. Active low, logic input. This input provides the dual function of initiating conversions on the AD7357 and framing the serial data transfer. 12 7 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7357. Connect this pin to the DGND plane of a system. The DGND and AGND voltages must ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 13, 14 8, 9 SDATAB, Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits SDATAA are clocked out on the falling edge of the SCLK input. 16 SCLK falling edges are required to access the 14 bits of data from the AD7357. The data simultaneously appears on both data output pins from the simultaneous conversions of both ADCs. The data stream consists of two leading zeros, followed by the 14 bits of conversion data. The data is provided MSB first. If CS is held low for 18 SCLK cycles rather than 16, then two trailing zeros appear after the 14 bits of data. If CS is held low for an additional 18 SCLK cycles on either SDATAA or SDATAB , the data from the other ADC follows on the SDATAx pins. This allows data from a simultaneous conversion on both ADCs to gather in serial format on either SDATAA or SDATAB. 15 10 SCLK Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7357. This clock is also used as the clock source for the conversion process. Rev. E | Page 8 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ANALOG INPUT STRUCTURE ANALOG INPUTS DRIVING DIFFERENTIAL INPUTS Differential Amplifier Operational Amplifier Pair VOLTAGE REFERENCE ADC TRANSFER FUNCTION MODES OF OPERATION NORMAL MODE PARTIAL POWER-DOWN MODE FULL POWER-DOWN MODE POWER-UP TIMES POWER vs. THROUGHPUT RATE SERIAL INTERFACE APPLICATION SUGGESTIONS GROUNDING AND LAYOUT EVALUATING THE AD7357 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS