Datasheet AD7264 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 1 MSPS, 14-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators |
| Pages / Page | 30 / 4 — Data Sheet. AD7264. SPECIFICATIONS. Table 1. Parameter. Min. Typ. Max. … |
| Revision | E |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
Data Sheet. AD7264. SPECIFICATIONS. Table 1. Parameter. Min. Typ. Max. Unit. Test Conditions/Comments
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Data Sheet AD7264 SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fS = 1 MSPS and fSCLK = 34 MHz for the AD7264, fS = 500 kSPS and fSCLK = 20 MHz for the AD7264-5, VREF = 2.5 V internal/external; TA = −40°C to +105°C, unless otherwise noted.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE1 fIN = 100 kHz sine wave Signal-to-Noise Ratio (SNR)2 76 78 dB PGA gain setting = 2 Signal-to-(Noise + Distortion) Ratio 74 77 dB (SINAD)2 Total Harmonic Distortion (THD)2 −85 −77 dB Spurious-Free Dynamic Range (SFDR) −97 dB Common-Mode Rejection Ratio (CMRR) −76 dB For PGA gain setting = 2, ripple frequency of 50 Hz/60 Hz; see Figure 17 and Figure 18 ADC-to-ADC Isolation2 −90 dB Bandwidth3 1.2 MHz At −3 dB; PGA gain setting = 128 1.7 MHz At −3 dB; PGA gain setting = 2 DC ACCURACY Resolution 14 Bits Integral Nonlinearity2 ±1.5 ±3 LSB Differential Nonlinearity2 ±0.5 ±0.99 LSB Guaranteed no missed codes to 14 bits Positive Full-Scale Error2 ±0.122 ±0.305 % FSR Precalibration ±0.018 % FSR Postcalibration Positive Full-Scale Error Match2 ±0.061 % FSR Zero Code Error2 ±0.092 ±0.244 % FSR Precalibration ±0.012 % FSR Postcalibration Zero Code Error Match2 ±0.061 % FSR Negative Full-Scale Error2 ±0.122 ±0.305 % FSR Precalibration ±0.018 % FSR Postcalibration Negative Full-Scale Error Match2 ±0.061 % FSR Zero Code Error Drift 2.5 µV/°C ANALOG INPUT Input Voltage Range, VIN+ and VIN− V V VCM = AVCC/2; PGA gain setting ≥ 2 V REF ± CM 2 × Gain Common-Mode Voltage Range, VCM VCM − 100 mV VCM + 100 mV V VCM = 2 V; PGA gain setting = 1; see Figure 194 VCM − 0.4 VCM + 0.2 V VCM = AVCC/2; PGA gain setting = 2 VCM − 0.4 VCM + 0.4 V VCM = AVCC/2; 3 ≤ PGA gain setting ≤ 32 VCM − 0.6 VCM + 0.8 V VCM = AVCC/2; PGA gain setting ≥ 48 DC Leakage Current ±0.001 ±1 µA Input Capacitance3 5 pF Input Impedance3 1 GΩ REFERENCE INPUT/OUTPUT Reference Output Voltage5 2.495 2.5 2.505 V 2.5 V ± 5 mV max at 25°C Reference Input Voltage 2.5 V DC Leakage Current ±0.3 ±1 µA External reference applied to Pin VREFA/Pin VREFB Input Capacitance3 20 pF VREFA, VREFB Output Impedance3 4 Ω Reference Temperature Coefficient 20 ppm/°C VREF Noise3 20 µV rms Rev. D | Page 3 of 29 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION COMPARATORS OPERATION ANALOG INPUTS Transfer Function VDRIVE REFERENCE TYPICAL CONNECTION DIAGRAMS Comparator Application Details APPLICATION DETAILS MODES OF OPERATION PIN DRIVEN MODE GAIN SELECTION POWER-DOWN MODES Power-Up Conditions CONTROL REGISTER ON-CHIP REGISTERS Writing to a Register Reading from a Register SERIAL INTERFACE CALIBRATION INTERNAL OFFSET CALIBRATION ADJUSTING THE OFFSET CALIBRATION REGISTER SYSTEM GAIN CALIBRATION APPLICATIONS INFORMATION GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7264 SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, CA_CBVCC = CC_CDVCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fS = 1 MSPS and fSCLK = 34 MHz for the AD7264, fS = 500 kSPS and fSCLK = 20 MHz for the AD7264-5, VREF = 2.5 V internal/external; TA = −40°C to +105°C, unless otherwise noted.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE1 fIN = 100 kHz sine wave Signal-to-Noise Ratio (SNR)2 76 78 dB PGA gain setting = 2 Signal-to-(Noise + Distortion) Ratio 74 77 dB (SINAD)2 Total Harmonic Distortion (THD)2 −85 −77 dB Spurious-Free Dynamic Range (SFDR) −97 dB Common-Mode Rejection Ratio (CMRR) −76 dB For PGA gain setting = 2, ripple frequency of 50 Hz/60 Hz; see Figure 17 and Figure 18 ADC-to-ADC Isolation2 −90 dB Bandwidth3 1.2 MHz At −3 dB; PGA gain setting = 128 1.7 MHz At −3 dB; PGA gain setting = 2 DC ACCURACY Resolution 14 Bits Integral Nonlinearity2 ±1.5 ±3 LSB Differential Nonlinearity2 ±0.5 ±0.99 LSB Guaranteed no missed codes to 14 bits Positive Full-Scale Error2 ±0.122 ±0.305 % FSR Precalibration ±0.018 % FSR Postcalibration Positive Full-Scale Error Match2 ±0.061 % FSR Zero Code Error2 ±0.092 ±0.244 % FSR Precalibration ±0.012 % FSR Postcalibration Zero Code Error Match2 ±0.061 % FSR Negative Full-Scale Error2 ±0.122 ±0.305 % FSR Precalibration ±0.018 % FSR Postcalibration Negative Full-Scale Error Match2 ±0.061 % FSR Zero Code Error Drift 2.5 µV/°C ANALOG INPUT Input Voltage Range, VIN+ and VIN− V V VCM = AVCC/2; PGA gain setting ≥ 2 V REF ± CM 2 × Gain Common-Mode Voltage Range, VCM VCM − 100 mV VCM + 100 mV V VCM = 2 V; PGA gain setting = 1; see Figure 194 VCM − 0.4 VCM + 0.2 V VCM = AVCC/2; PGA gain setting = 2 VCM − 0.4 VCM + 0.4 V VCM = AVCC/2; 3 ≤ PGA gain setting ≤ 32 VCM − 0.6 VCM + 0.8 V VCM = AVCC/2; PGA gain setting ≥ 48 DC Leakage Current ±0.001 ±1 µA Input Capacitance3 5 pF Input Impedance3 1 GΩ REFERENCE INPUT/OUTPUT Reference Output Voltage5 2.495 2.5 2.505 V 2.5 V ± 5 mV max at 25°C Reference Input Voltage 2.5 V DC Leakage Current ±0.3 ±1 µA External reference applied to Pin VREFA/Pin VREFB Input Capacitance3 20 pF VREFA, VREFB Output Impedance3 4 Ω Reference Temperature Coefficient 20 ppm/°C VREF Noise3 20 µV rms Rev. D | Page 3 of 29 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION COMPARATORS OPERATION ANALOG INPUTS Transfer Function VDRIVE REFERENCE TYPICAL CONNECTION DIAGRAMS Comparator Application Details APPLICATION DETAILS MODES OF OPERATION PIN DRIVEN MODE GAIN SELECTION POWER-DOWN MODES Power-Up Conditions CONTROL REGISTER ON-CHIP REGISTERS Writing to a Register Reading from a Register SERIAL INTERFACE CALIBRATION INTERNAL OFFSET CALIBRATION ADJUSTING THE OFFSET CALIBRATION REGISTER SYSTEM GAIN CALIBRATION APPLICATIONS INFORMATION GROUNDING AND LAYOUT PCB DESIGN GUIDELINES FOR LFCSP OUTLINE DIMENSIONS ORDERING GUIDE
