Datasheet AD7991, AD7995, AD7999 (Analog Devices) - 4

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AD7991/AD7995/AD7999 Y Version Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS (SDA, SCL) Input High Voltage, VINH 0.7 (VDD) V VDD = 2.7 V to 5.5 V 0.9 (VDD) V VDD = 2.35 V to 2.7 V Input Low Voltage, VINL 0.3 (VDD) V VDD = 2.7 V to 5.5 V 0.1 (VDD) V VDD = 2.35 V to 2.7 V Input Leakage Current, IIN ±1 μA VIN = 0 V or VDD Input Capacitance, C 6 IN 10 pF Input Hysteresis, VHYST 0.1 (VDD) V LOGIC OUTPUTS (OPEN DRAIN) Output Low Voltage, VOL 0.4 V ISINK = 3 mA 0.6 V ISINK = 6 mA Floating-State Leakage Current ±1 μA Floating-State Output Capacitance6 10 pF Output Coding Straight (natural) binary THROUGHPUT RATE 18 × (1/fSCL) fSCL ≤ 1.7 MHz; see the Serial Interface section 17.5 × (1/fSCL) fSCL > 1.7 MHz; see the Serial Interface + 2 μs section POWER REQUIREMENTS2 VREF = VDD; for fSCL = 3.4 MHz, clock stretching is implemented VDD 2.7 5.5 V IDD Digital inputs = 0 V or VDD ADC Operating, Interface Active 0.09/0.25 mA VDD = 3.3 V/5.5 V, 400 kHz fSCL (Fully Operational) 0.25/0.8 mA VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Power-Down, Interface Active7 0.07/0.16 mA VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.26/0.85 mA VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Power-Down, Interface Inactive7 1/1.6 μA VDD = 3.3 V/5.5 V Power Dissipation ADC Operating, Interface Active 0.3/1.38 mW VDD = 3.3 V/5.5 V, 400 kHz fSCL (Fully Operational) 0.83/4.4 mW VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Power-Down, Interface Active7 0.24/0.88 mW VDD = 3.3 V/5.5 V, 400 kHz fSCL 0.86/4.68 mW VDD = 3.3 V/5.5 V, 3.4 MHz fSCL Power-Down, Interface Inactive7 3.3/8.8 μW VDD = 3.3 V/5.5 V 1 Functional from VDD = 2.35 V. 2 Sample delay and bit trial delay enabled, t1 = t2 = 0.5/fSCL. 3 For fSCL up to 400 kHz, clock stretching is not implemented. Above fSCL = 400 kHz, clock stretching is implemented. 4 See the Terminology section. 5 For fSCL ≤ 1.7 MHz, clock stretching is not implemented; for fSCL > 1.7 MHz, clock stretching is implemented. 6 Guaranteed by initial characterization. 7 See the Reading from the AD7991/AD7995/AD7999 section. Rev. B | Page 4 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7991 AD7995 AD7999 I2C TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CONVERTER OPERATION ADC Transfer Function TYPICAL CONNECTION DIAGRAM ANALOG INPUT INTERNAL REGISTER STRUCTURE CONFIGURATION REGISTER SAMPLE DELAY AND BIT TRIAL DELAY CONVERSION RESULT REGISTER SERIAL INTERFACE SERIAL BUS ADDRESS WRITING TO THE AD7991/AD7995/AD7999 READING FROM THE AD7991/AD7995/AD7999 PLACING THE AD7991/AD7995/AD7999 INTO HIGH SPEED MODE MODE OF OPERATION OUTLINE DIMENSIONS ORDERING GUIDE