Datasheet AD9600 (Analog Devices) - 10

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AD9600 SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.
Table 4. AD9600ABCPZ-105/ AD9600ABCPZ-125/ AD9600ABCPZ-150/ AD9600BCPZ-105 AD9600BCPZ-125 AD9600BCPZ-150 Parameter Temp Min Typ Max Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS Input Clock Rate Full 625 625 625 MHz Conversion Rate DCS Enabled Full 20 105 20 125 20 150 MSPS DCS Disabled Full 10 105 10 125 10 150 MSPS CLK Period (tCLK) Full 9.5 8 6.66 ns CLK Pulse Width High Divide-by-1 Mode, Full 2.85 4.75 6.65 2.4 4 5.6 2.0 3.33 4.66 ns DCS Enabled Divide-by-1 Mode, Full 4.28 4.75 5.23 3.6 4 4.4 3.0 3.33 3.66 ns DCS Disabled Divide-by-2 Mode, Full 1.6 1.6 1.6 ns DCS Enabled Divide-by-3 Through Divide- Full 0.8 0.8 0.8 ns by-8 Modes, DCS Enabled DATA OUTPUT PARAMETERS CMOS Mode—DRVDD = 3.3 V Data Propagation Delay (tPD)1 Full 2.2 4.5 6.4 2.2 4.5 6.4 2.2 4.5 6.4 ns DCO Propagation Delay (tDCO) Full 3.8 5.0 6.8 3.8 5.0 6.8 3.8 5.0 6.8 ns Setup Time (tS) Full 5.25 4.5 3.83 ns Hold Time (tH) Full 4.25 3.5 2.83 ns CMOS Mode—DRVDD = 1.8 V Data Propagation Delay (tPD)1 Full 2.4 5.2 6.9 2.4 5.2 6.9 2.4 5.2 6.9 ns DCO Propagation Delay (tDCO) Full 4.0 5.6 7.3 4.0 5.6 7.3 4.0 5.6 7.3 ns Setup Time (tS) Full 5.25 4.5 3.83 ns Hold Time (tH) Full 4.25 3.5 2.83 ns LVDS Mode—DRVDD = 1.8 V Data Propagation Delay (tPD)1 Full 3.0 3.7 4.4 3.0 3.8 4.5 3.0 3.8 4.5 ns DCO Propagation Delay (tDCO) Full 5.2 6.4 7.6 5.0 6.2 7.4 4.8 5.9 7.3 ns CMOS Mode Pipeline Delay Full 12 12 12 Cycles (Latency) LVDS Mode Pipeline Delay Full 12/12.5 12/12.5 12/12.5 Cycles (Latency) Channel A/Channel B Aperture Delay (tA) Full 1.0 1.0 1.0 ns Aperture Uncertainty (Jitter, tJ) Full 0.1 0.1 0.1 ps rms Wake-Up Time2 Full 350 350 350 μs OUT-OF-RANGE RECOVERY TIME Full 2 3 3 Cycles 1 Output propagation delay is measured from the CLK+ and CLK− pins 50% transition to the output data pins 50% transition, with 5 pF load. 2 Wake-up time is dependent on the value of the decoupling capacitors. Rev. B | Page 9 of 72 Document Outline FEATURES APPLICATIONS PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) ADC OVERRANGE AND GAIN CONTROL FAST DETECT OVERVIEW ADC FAST MAGNITUDE ADC OVERRANGE (OR) GAIN SWITCHING Coarse Upper Threshold (C_UT) Fine Upper Threshold (F_UT) Fine Lower Threshold (F_LT) Increment Gain (IG) and Decrement Gain (DG) SIGNAL MONITOR PEAK DETECTOR MODE RMS/MS MAGNITUDE MODE THRESHOLD CROSSING MODE ADDITIONAL CONTROL BITS Signal Monitor Enable Bit Complex Power Calculation Mode Enable Bit DC CORRECTION DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction Enable Bits SIGNAL MONITOR SPORT OUTPUT SMI SCLK SMI SDFS SMI SDO BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES CHANNEL/CHIP SYNCHRONIZATION SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers MEMORY MAP MEMORY MAP REGISTER DESCRIPTION Sync Control (Register 0x100) Bit 7—Signal Monitor Sync Enable Bits [6:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable Fast Detect Control (Register 0x104) Bits [7:4]—Reserved Bits [3:1]—Fast Detect Mode Select Bit 0—Fast Detect Enable Coarse Upper Threshold (Register 0x105) Bits [7:3]—Reserved Bits [2:0]—Coarse Upper Threshold Fine Upper Threshold (Register 0x106 and Register 0x107) Register 0x106, Bits [7:0]—Fine Upper Threshold [7:0] Register 0x107, Bits [7:5]—Reserved Register 0x107, Bits [4:0]—Fine Upper Threshold [12:8] Fine Lower Threshold (Register 0x108 and Register 0x109) Register 0x108, Bits [7:0]—Fine Lower Threshold [7:0]Register 0x109, Bits [7:5]—ReservedRegister 0x109, Bits [4:0]—Fine Lower Threshold [12:8] Increase Gain Dwell Time (Register 0x10A andRegister 0x10B) Register 0x10A, Bits [7:0]—Increase Gain Dwell Time [7:0]Register 0x10B, Bits [7:0]—Increase Gain Dwell Time [15:8] Signal Monitor DC Correction Control (Register 0x10C) Bit 7—ReservedBit 6—DC Correction Freeze Bits [5:2]—DC Correction Bandwidth Bit 1—DC Correction for Signal Path Enable Bit 0—DC Correction for Signal Monitor Enable Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E) Register 0x10D, Bits [7:0]—DC Value Channel A [7:0] Register 0x10E, Bits [7:6]—Reserved Register 0x10E, Bits [5:0]—DC Value Channel A [13:8] Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110) Register 0x10F Bits [7:0]—DC Value Channel B [7:0] Register 0x110 Bits [7:6]—Reserved Register 0x110 Bits [5:0]—DC Value Channel B [13:8] Signal Monitor SPORT Control (Register 0x111) Bit 7—Reserved Bit 6—RMS/MS Magnitude Output Enable Bit 5—Peak Detector Output Enable Bit 4—Threshold Crossing Output Enable Bits [3:2]—SPORT SMI SCLK Divide Bit 1— SPORT SMI SCLK Sleep Bit 0—Signal Monitor SPORT Output Enable Signal Monitor Control (Register 0x112) Bit 7—Complex Power Calculation Mode Enable Bits [6:4]—Reserved Bit 3—Signal Monitor RMS/MS Select Bits [2:1]—Signal Monitor Mode Bit 0—Signal Monitor Enable Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits [7:0]—Signal Monitor Period [7:0] Register 0x114, Bits [7:0]—Signal Monitor Period [15:8] Register 0x115, Bits [7:0]—Signal Monitor Period [23:16] Signal Monitor Result Channel A (Register 0x116 to Register 0x118) Register 0x116, Bits [7:0]—Signal Monitor Result Channel A [7:0] Register 0x117, Bits [7:0]—Signal Monitor Result Channel A [15:8] Register 0x118, Bits [7:4]—Reserved Register 0x118, Bits [3:0]—Signal Monitor Result Channel A [19:16] Signal Monitor Result Channel B (Register 0x119 to Register 0x11B) Register 0x119, Bits [7:0]— Signal Monitor Result Channel B [7:0] Register 0x11A, Bits [7:0]—Signal Monitor Result Channel B [15:8] Register 0x11B, Bits [7:4]—Reserved Register 0x11B, Bits [3:0]—Signal Monitor Result Channel B [19:16] APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS Reference Decoupling SPI Port EVALUATION BOARD POWER SUPPLIES INPUT SIGNALS OUTPUT SIGNALS DEFAULT OPERATION AND JUMPER SELECTION SETTINGS POWER VIN RBIAS CLOCK PDWN CSB SCLK/DFS SDIO/DCS ALTERNATIVE CLOCK CONFIGURATIONS ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION SCHEMATICS EVALUATION BOARD LAYOUTS BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE