Datasheet AD9640 (Analog Devices)

14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9640 FEATURES FUNCTIONAL BLOCK DIAGRAM SNR = 71.8 dBc (72.8 dBFS) to 70 MHz @ 125 MSPS SDIO/ SCLK/ AVDD DVDD FD(0:3)A DCS DFS CSB DRVDD SFDR = 85 dBc to 70 MHz @ 125 MSPS Low power: 750 mW @ 125 MSPS R FD BITS/THRESHOLD SPI E F SNR = 71.6 dBc (72.6 dBFS) to 70 MHz @ 150 MSPS DETECT F S D13A O BU SFDR = 84 dBc to 70 MHz @ 150 MSPS PROGRAMMING DATA CM UT P D0A Low power: 820 mW @ 150 MSPS VIN+A SHA ADC UT 1.8 V analog supply operation O VIN–A SIGNAL 1.8 V to 3.3V CMOS output supply or 1.8 V LVDS CLK+ MONITOR VREF output supply CLK– SENSE DIVIDE Integer 1 to 8 input clock divider DCOA 1 TO 8 DCO IF sampling frequencies to 450 MHz CML REF GENERATION DCOB SELECT Internal ADC voltage reference DUTY CYCLE RBIAS STABILIZER R D13B E Integrated ADC sample-and-hold inputs F S Flexible analog input range: 1 V p-p to 2 V p-p VIN–B D0B O BUF SHA ADC Differential analog inputs with 650 MHz bandwidth CM UT VIN+B P SIGNAL MONITOR T ADC clock duty cycle stabilizer U DATA O 95 dB channel isolation/crosstalk MULTICHIP FD BITS/THRESHOLD SIGNAL MONITOR Serial port control SYNC DETECT INTERFACE User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes
001
AGND SYNC FD(0:3)B SMI SMI SMI DRGND Integrated receive features SDFS SCLK/ SDO/
06547-
PDWN OEB Fast detect/threshold bits
Figure 1.
Composite signal monitor PRODUCT HIGHLIGHTS APPLICATIONS
1. Integrated dual 14-bit, 80/105/125/150 MSPS ADC.
Communications
2. Fast overrange detect and signal monitor with serial output.
Diversity radio systems
3. Signal monitor block with dedicated serial output mode.
Multimode digital receivers
4. Proprietary differential input that maintains excellent SNR
GSM, EDGE, WCDMA, LTE,
performance for input frequencies up to 450 MHz.
CDMA2000, WiMAX, TD-SCDMA
5. Operation from a single 1.8 V supply and a separate digital
I/Q demodulation systems
output driver supply to accommodate 1.8 V to 3.3 V logic
Smart antenna systems
families.
General-purpose software radios
6. A standard serial port interface that supports various
Broadband data applications
product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, and voltage reference mode. 7. Pin compatibility with the AD9627, AD9627-11, and the AD9600 for a simple migration from 14 bits to 12 bits, 11 bits, or 10 bits.
Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105 ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ150 ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ80, AD9640ABCPZ-105, AND AD9640BCPZ-105 ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ125, AD9640ABCPZ-150, AND AD9640BCPZ 150 DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ105 SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ150 TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) ADC OVERRANGE AND GAIN CONTROL FAST DETECT OVERVIEW ADC FAST MAGNITUDE ADC OVERRANGE (OR) GAIN SWITCHING Coarse Upper Threshold (C_UT) Fine Upper Threshold (F_UT) Fine Lower Threshold (F_LT) Increment Gain (IG) and Decrement Gain (DG) SIGNAL MONITOR PEAK DETECTOR MODE RMS/MS MAGNITUDE MODE THRESHOLD CROSSING MODE ADDITIONAL CONTROL BITS Signal Monitor Enable Bit Complex Power Calculation Mode Enable Bit DC CORRECTION DC Correction Bandwidth DC Correction Readback DC Correction Freeze DC Correction Enable Bits SIGNAL MONITOR SPORT OUTPUT SMI SCLK SMI SDFS SMI SDO BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES CHANNEL/CHIP SYNCHRONIZATION SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP TABLE Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers EXTERNAL MEMORY MAP MEMORY MAP REGISTER DESCRIPTION Sync Control (Register 0x100) Bit 7—Signal Monitor Sync Enable Bits[6:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable Fast Detect Control (Register 0x104) Bits[7:4]—Reserved Bits[3:1]—Fast Detect Mode Select Bit 0—Fast Detect Enable Fine Upper Threshold (Register 0x106 and Register 0x107) Register 0x106, Bits[7:0]—Fine Upper Threshold[7:0] Register 0x107, Bits[7:5]—Reserved Register 0x107, Bits[4:0]—Fine Upper Threshold[12:8] Fine Lower Threshold (Register 0x108 and Register 0x109) Register 0x108, Bits[7:0]—Fine Lower Threshold[7:0]Register 0x109, Bits[7:5]—ReservedRegister 0x109, Bits[4:0]—Fine Lower Threshold[12:8] Signal Monitor DC Correction Control (Register 0x10C) Bit 7—ReservedBit 6—DC Correction Freeze Bits[5:2]—DC Correction Bandwidth Bit 1—DC Correction for Signal Path Enable Bit 0—DC Correction for SM Enable Signal Monitor DC Value Channel A (Register 0x10D and Register 0x10E) Register 0x10D, Bits[7:0]—Channel A DC Value[7:0] Register 0x10E, Bits[7:0]—Channel A DC Value[13:8] Signal Monitor DC Value Channel B (Register 0x10F and Register 0x110) Register 0x10F Bits[7:0]—Channel B DC Value[7:0] Register 0x110 Bits[7:0]—Channel B DC Value[13:8] Signal Monitor SPORT Control (Register 0x111) Bit 7—Reserved Bit 6—RMS/MS Magnitude Output Enable Bit 5—Peak Power Output Enable Bit 4—Threshold Crossing Output Enable Bits[3:2]—SPORT SMI SCLK Divide Bit 1— SPORT SMI SCLK Sleep Bit 0—Signal Monitor SPORT Output Enable Signal Monitor Control (Register 0x112) Bit 7—Complex Power Calculation Mode Enable Bits[6:4]—Reserved Bit 3—Signal Monitor RMS/MS Select Bits[2:1]—Signal Monitor Mode Bit 0—Signal Monitor Enable Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits[7:0]—Signal Monitor Period[7:0] Register 0x114, Bits[7:0]—Signal Monitor Period[15:8] Register 0x115, Bits[7:0]—Signal Monitor Period[23:16] Signal Monitor Result Channel A (Register 0x116 to Register 0x118) Register 0x116, Bits[7:0]—Signal Monitor Result Channel A[7:0] Register 0x117, Bits[7:0]—Signal Monitor Result Channel A[15:8] Register 0x118, Bits[7:4]—Reserved Register 0x118, Bits[3:0]—Signal Monitor Result Channel A[19:16] Signal Monitor Result Channel B (Register 0x119 to Register 0x11B) Register 0x119, Bits[7:0]— Signal Monitor Result Channel B[7:0] Register 0x11A, Bits[7:0]—Signal Monitor Result Channel B[15:8] Register 0x11B, Bits[7:4]—Reserved Register 0x11B, Bits[3:0]—Signal Monitor Result Channel B[19:16] APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations LVDS Operation Exposed Paddle Thermal Heat Slug Recommendations CML RBIAS Reference Decoupling SPI Port OUTLINE DIMENSIONS ORDERING GUIDE