Datasheet AD7612 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 16-Bit, 750 kSPS, Unipolar/Bipolar Programmable Input PulSAR ADC |
| Pages / Page | 33 / 9 — AD7612. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. BUF. … |
| Revision | A |
| File Format / Size | PDF / 590 Kb |
| Document Language | English |
AD7612. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. BUF. DBUF. DRE. VEE. 48 47 46 45 44 43 42 41 40 39 38 37. AGND 1
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AD7612 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN F ND BUF P G F M DD ND C F F DBUF DRE + – P P RE TE AV IN AG VEE VC IN RE RE 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 BIPOLAR AVDD PIN 1 2 35 CNVST AGND 3 34 PD BYTESWAP 4 33 RESET OB/2C 5 32 CS AD7612 WARP 6 31 RD TOP VIEW IMPULSE 7 30 (Not to Scale) TEN SER/PAR 8 29 BUSY D0 9 28 D15/SCCS D1 10 27 D14/SCCLK D2/DIVSCLK[0] 11 26 D13/SCIN D3/DIVSCLK[1] 12 25 D12/HW/SW 13 14 15 16 17 18 19 20 21 22 23 24 T C IN D D K C R /IN LK D N D DD ND UT T C S X S OV DV DO DCL VSYN V OG DG S S RRO 4/E 10/SYN D 5/IN 6/IN RDC/ D8/ D9/ D RDE D D D7/ 1/ D1 NOTES
04
1. FOR THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP), THE EXPOSED
0 5-
PAD SHOULD BE CONNECTED TO VEE. THIS CONNECTION IS NOT
626
REQUIRED TO MEET THE ELECTRICAL PERFORMANCES.
0 Figure 4. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1, 3, 42 AGND P Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be referenced to AGND and should be connected to the analog ground plane of the system. In addition, the AGND, DGND, and OGND voltages should be at the same potential. 2, 44 AVDD P Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. 4 BYTESWAP DI Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8]. 5 OB/2C DI2 Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary. When low, the MSB is inverted resulting in a twos complement output from its internal shift register. 6 WARP DI2 Conversion Mode Selection. Used in conjunction with the IMPULSE input per the following:
Conversion Mode WARP IMPULSE
Normal Low Low Impulse Low High Warp High Low Normal High High See the Modes of Operation section for a more detailed description. 7 IMPULSE DI2 Conversion Mode Selection. See the WARP pin description in the previous row of this table. See the Modes of Operation section for a more detailed description. 8 SER/PAR DI Serial/Parallel Selection Input. When SER/PAR = low, the parallel mode is selected. When SER/PAR = high, the serial modes are selected. Some bits of the data bus are used as a serial port and the remaining data bits are high impedance outputs. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the parallel port data output bus. These pins are always outputs regardless of the state of SER/PAR. Rev. A | Page 8 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION OVERVIEW CONVERTER OPERATION MODES OF OPERATION Normal Mode Impulse Mode TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS Input Range Selection Input Structure VOLTAGE REFERENCE INPUT/OUTPUT Internal Reference (REF = 5 V) (PDREF = Low, PDBUF = Low) External 2.5 V Reference and Internal Buffer (REF = 5 V) (PDREF = High, PDBUF = Low) External 5 V Reference (PDREF = High, PDBUF = High) Reference Decoupling Temperature Sensor POWER SUPPLIES Core Supplies High Voltage Supplies Digital Output Supply Power Sequencing Power Dissipation vs. Throughput Power Down CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) SERIAL INTERFACE Data Interface MASTER SERIAL INTERFACE Internal Clock (SER/ = high, EXT/ = Low) Read During Convert (RDC = High) Read During Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) SLAVE SERIAL INTERFACE External Clock (SER/ = High, EXT/ = High) External Discontinuous Clock Data Read After Conversion Daisy-Chain Feature External Clock Data Read During Previous Conversion External Clock Data Read After/During Conversion HARDWARE CONFIGURATION SOFTWARE CONFIGURATION MICROPROCESSOR INTERFACING SPI Interface APPLICATION INFORMATION LAYOUT GUIDELINES EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
AD7612 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IN F ND BUF P G F M DD ND C F F DBUF DRE + – P P RE TE AV IN AG VEE VC IN RE RE 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 BIPOLAR AVDD PIN 1 2 35 CNVST AGND 3 34 PD BYTESWAP 4 33 RESET OB/2C 5 32 CS AD7612 WARP 6 31 RD TOP VIEW IMPULSE 7 30 (Not to Scale) TEN SER/PAR 8 29 BUSY D0 9 28 D15/SCCS D1 10 27 D14/SCCLK D2/DIVSCLK[0] 11 26 D13/SCIN D3/DIVSCLK[1] 12 25 D12/HW/SW 13 14 15 16 17 18 19 20 21 22 23 24 T C IN D D K C R /IN LK D N D DD ND UT T C S X S OV DV DO DCL VSYN V OG DG S S RRO 4/E 10/SYN D 5/IN 6/IN RDC/ D8/ D9/ D RDE D D D7/ 1/ D1 NOTES
04
1. FOR THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP), THE EXPOSED
0 5-
PAD SHOULD BE CONNECTED TO VEE. THIS CONNECTION IS NOT
626
REQUIRED TO MEET THE ELECTRICAL PERFORMANCES.
0 Figure 4. Pin Configuration
Table 6. Pin Function Descriptions Pin No. Mnemonic Type1 Description
1, 3, 42 AGND P Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be referenced to AGND and should be connected to the analog ground plane of the system. In addition, the AGND, DGND, and OGND voltages should be at the same potential. 2, 44 AVDD P Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. 4 BYTESWAP DI Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8]. 5 OB/2C DI2 Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary. When low, the MSB is inverted resulting in a twos complement output from its internal shift register. 6 WARP DI2 Conversion Mode Selection. Used in conjunction with the IMPULSE input per the following:
Conversion Mode WARP IMPULSE
Normal Low Low Impulse Low High Warp High Low Normal High High See the Modes of Operation section for a more detailed description. 7 IMPULSE DI2 Conversion Mode Selection. See the WARP pin description in the previous row of this table. See the Modes of Operation section for a more detailed description. 8 SER/PAR DI Serial/Parallel Selection Input. When SER/PAR = low, the parallel mode is selected. When SER/PAR = high, the serial modes are selected. Some bits of the data bus are used as a serial port and the remaining data bits are high impedance outputs. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the parallel port data output bus. These pins are always outputs regardless of the state of SER/PAR. Rev. A | Page 8 of 32 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION OVERVIEW CONVERTER OPERATION MODES OF OPERATION Normal Mode Impulse Mode TRANSFER FUNCTIONS TYPICAL CONNECTION DIAGRAM ANALOG INPUTS Input Range Selection Input Structure VOLTAGE REFERENCE INPUT/OUTPUT Internal Reference (REF = 5 V) (PDREF = Low, PDBUF = Low) External 2.5 V Reference and Internal Buffer (REF = 5 V) (PDREF = High, PDBUF = Low) External 5 V Reference (PDREF = High, PDBUF = High) Reference Decoupling Temperature Sensor POWER SUPPLIES Core Supplies High Voltage Supplies Digital Output Supply Power Sequencing Power Dissipation vs. Throughput Power Down CONVERSION CONTROL INTERFACES DIGITAL INTERFACE RESET PARALLEL INTERFACE Master Parallel Interface Slave Parallel Interface 8-Bit Interface (Master or Slave) SERIAL INTERFACE Data Interface MASTER SERIAL INTERFACE Internal Clock (SER/ = high, EXT/ = Low) Read During Convert (RDC = High) Read During Convert (RDC = Low, DIVSCLK[1:0] = [0 to 3]) SLAVE SERIAL INTERFACE External Clock (SER/ = High, EXT/ = High) External Discontinuous Clock Data Read After Conversion Daisy-Chain Feature External Clock Data Read During Previous Conversion External Clock Data Read After/During Conversion HARDWARE CONFIGURATION SOFTWARE CONFIGURATION MICROPROCESSOR INTERFACING SPI Interface APPLICATION INFORMATION LAYOUT GUIDELINES EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
