Datasheet AD9259 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Quad, 14-Bit, 50 MSPS Serial LVDS 1.8 V ADC |
| Pages / Page | 53 / 5 — AD9259. Data Sheet. SPECIFICATIONS. Table 1. Parameter. Temperature. Min. … |
| Revision | E |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
AD9259. Data Sheet. SPECIFICATIONS. Table 1. Parameter. Temperature. Min. Typ. Max. Unit
Model Line for this Datasheet
Text Version of Document
link to page 6 link to page 6 link to page 6 link to page 5 link to page 5 link to page 5
AD9259 Data Sheet SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 1. Parameter 1 Temperature Min Typ Max Unit
RESOLUTION 14 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error Full ±1 ±8 mV Offset Matching Full ±2 ±8 mV Gain Error Full ±0.5 ±2 % FS Gain Matching Full ±0.3 ±0.7 % FS Differential Nonlinearity (DNL) Full ±0.5 ±1.0 LSB Integral Nonlinearity (INL) Full ±1.5 ±3.5 LSB TEMPERATURE DRIFT Offset Error Full ±2 ppm/°C Gain Error Full ±17 ppm/°C Reference Voltage (1 V Mode) Full ±21 ppm/°C REFERENCE Output Voltage Error (VREF = 1 V) Full ±5 ±30 mV Load Regulation at 1.0 mA (VREF = 1 V) Full 3 mV Input Resistance Full 6 kΩ ANALOG INPUTS Differential Input Voltage (VREF = 1 V) Full 2 V p-p Common-Mode Voltage Full AVDD/2 V Differential Input Capacitance Full 7 pF Analog Bandwidth, Full Power Full 315 MHz POWER SUPPLY AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V IAVDD Full 185 192.5 mA IDRVDD Full 32.5 34.7 mA Total Power Dissipation (Including Output Drivers) Full 392 409 mW Power-Down Dissipation Full 2 4 mW Standby Dissipation2 Full 72 mW CROSSTALK Full −100 dB CROSSTALK (Overrange Condition)3 Full −100 dB 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were completed. 2 Can be controlled via the SPI. 3 Overrange condition is specific with 6 dB of the ful -scale input range. Rev. E | Page 4 of 52 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide
AD9259 Data Sheet SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 1. Parameter 1 Temperature Min Typ Max Unit
RESOLUTION 14 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error Full ±1 ±8 mV Offset Matching Full ±2 ±8 mV Gain Error Full ±0.5 ±2 % FS Gain Matching Full ±0.3 ±0.7 % FS Differential Nonlinearity (DNL) Full ±0.5 ±1.0 LSB Integral Nonlinearity (INL) Full ±1.5 ±3.5 LSB TEMPERATURE DRIFT Offset Error Full ±2 ppm/°C Gain Error Full ±17 ppm/°C Reference Voltage (1 V Mode) Full ±21 ppm/°C REFERENCE Output Voltage Error (VREF = 1 V) Full ±5 ±30 mV Load Regulation at 1.0 mA (VREF = 1 V) Full 3 mV Input Resistance Full 6 kΩ ANALOG INPUTS Differential Input Voltage (VREF = 1 V) Full 2 V p-p Common-Mode Voltage Full AVDD/2 V Differential Input Capacitance Full 7 pF Analog Bandwidth, Full Power Full 315 MHz POWER SUPPLY AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V IAVDD Full 185 192.5 mA IDRVDD Full 32.5 34.7 mA Total Power Dissipation (Including Output Drivers) Full 392 409 mW Power-Down Dissipation Full 2 4 mW Standby Dissipation2 Full 72 mW CROSSTALK Full −100 dB CROSSTALK (Overrange Condition)3 Full −100 dB 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were completed. 2 Can be controlled via the SPI. 3 Overrange condition is specific with 6 dB of the ful -scale input range. Rev. E | Page 4 of 52 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input Considerations Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO/ODM Pin SCLK/DTP Pin CSB Pin RBIAS Pin Voltage Reference Internal Reference Operation External Reference Operation Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Evaluation Board Power Supplies Input Signals Output Signals Default Operation and Jumper Selection Settings Alternative Analog Input Drive Configuration Outline Dimensions Ordering Guide
