Datasheet AD7829-1 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 3 V/5 V, 2 MSPS, 8-Bit, 8-Channel ADC |
| Pages / Page | 21 / 6 — AD7829-1. TIMING CHARACTERISTICS. Table 2. Parameter. 1, 2. 10%. 3 V. … |
| File Format / Size | PDF / 364 Kb |
| Document Language | English |
AD7829-1. TIMING CHARACTERISTICS. Table 2. Parameter. 1, 2. 10%. 3 V. Unit. Description. TIMING DIAGRAM. 200µA. IOL. TO OUTPUT. 2.1V. PIN. 50pF
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AD7829-1 TIMING CHARACTERISTICS
VREF IN/OUT = 2.5 V. All specifications −40°C to +85°C, unless otherwise noted.
Table 2. Parameter 1, 2 5 V
±
10% 3 V
±
10% Unit Description
t1 420 420 ns max Conversion time t2 20 20 ns min Minimum CONVST pulse width t3 30 30 ns min Minimum time between the rising edge of RD and the next falling edge of convert start t4 110 110 ns max EOC pulse width 70 70 ns min t5 10 10 ns max RD rising edge to EOC pulse high t6 0 0 ns min CS to RD setup time t7 0 0 ns min CS to RD hold time t8 30 30 ns min Minimum RD pulse width t 3 9 10 20 ns max Data access time after RD low t 4 10 5 5 ns min Bus relinquish time after RD high 20 20 ns max t11 10 10 ns min Address setup time before the falling edge of RD t12 15 15 ns min Address hold time after the falling edge of RD t13 200 200 ns min Minimum time between new channel selection and convert start tPOWER UP 25 25 μs typ Power-up time from the rising edge of CONVST using on-chip reference tPOWER UP 1 1 μs max Power-up time from the rising edge of CONVST using external 2.5 V reference 1 Sample tested to ensure compliance. 2 See Figure 21, Figure 22, and Figure 23. 3 Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V with VDD = 5 V ± 10%, and the time required for an output to cross 0.4 V or 2.0 V with VDD = 3 V ± 10%. 4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish time of the part and, as such, is independent of external bus loading capacitances.
TIMING DIAGRAM 200µA IOL TO OUTPUT 2.1V PIN CL 50pF
2
200µA I
-00
OH
79 061 Figure 2. Load Circuit for Access Time and Bus Relinquish Time Rev. 0 | Page 5 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY CIRCUIT INFORMATION CIRCUIT DESCRIPTION TYPICAL CONNECTION DIAGRAM ADC TRANSFER FUNCTION ANALOG INPUT POWER-UP TIMES POWER VS. THROUGHPUT OPERATING MODES PARALLEL INTERFACE MICROPROCESSOR INTERFACING AD7829-1 TO 8051 AD7829-1 TO PIC16C6x/PIC16C7x AD7829-1 TO ADSP-21xx INTERFACING MULTIPLEXER ADDRESS INPUTS OUTLINE DIMENSIONS ORDERING GUIDE
AD7829-1 TIMING CHARACTERISTICS
VREF IN/OUT = 2.5 V. All specifications −40°C to +85°C, unless otherwise noted.
Table 2. Parameter 1, 2 5 V
±
10% 3 V
±
10% Unit Description
t1 420 420 ns max Conversion time t2 20 20 ns min Minimum CONVST pulse width t3 30 30 ns min Minimum time between the rising edge of RD and the next falling edge of convert start t4 110 110 ns max EOC pulse width 70 70 ns min t5 10 10 ns max RD rising edge to EOC pulse high t6 0 0 ns min CS to RD setup time t7 0 0 ns min CS to RD hold time t8 30 30 ns min Minimum RD pulse width t 3 9 10 20 ns max Data access time after RD low t 4 10 5 5 ns min Bus relinquish time after RD high 20 20 ns max t11 10 10 ns min Address setup time before the falling edge of RD t12 15 15 ns min Address hold time after the falling edge of RD t13 200 200 ns min Minimum time between new channel selection and convert start tPOWER UP 25 25 μs typ Power-up time from the rising edge of CONVST using on-chip reference tPOWER UP 1 1 μs max Power-up time from the rising edge of CONVST using external 2.5 V reference 1 Sample tested to ensure compliance. 2 See Figure 21, Figure 22, and Figure 23. 3 Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V with VDD = 5 V ± 10%, and the time required for an output to cross 0.4 V or 2.0 V with VDD = 3 V ± 10%. 4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish time of the part and, as such, is independent of external bus loading capacitances.
TIMING DIAGRAM 200µA IOL TO OUTPUT 2.1V PIN CL 50pF
2
200µA I
-00
OH
79 061 Figure 2. Load Circuit for Access Time and Bus Relinquish Time Rev. 0 | Page 5 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY CIRCUIT INFORMATION CIRCUIT DESCRIPTION TYPICAL CONNECTION DIAGRAM ADC TRANSFER FUNCTION ANALOG INPUT POWER-UP TIMES POWER VS. THROUGHPUT OPERATING MODES PARALLEL INTERFACE MICROPROCESSOR INTERFACING AD7829-1 TO 8051 AD7829-1 TO PIC16C6x/PIC16C7x AD7829-1 TO ADSP-21xx INTERFACING MULTIPLEXER ADDRESS INPUTS OUTLINE DIMENSIONS ORDERING GUIDE
