Data SheetAD7762TERMINOLOGY Signal-to-Noise Ratio (SNR)Differential Nonlinearity (DNL) SNR is the ratio of the rms value of the actual input signal to the The difference between the measured and the ideal 1-LSB rms sum of all other spectral components below the Nyquist change between any two adjacent codes in the ADC. frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Zero Error The zero error is the difference between the ideal midscale Total Harmonic Distortion (THD) input voltage (0 V) and the actual voltage producing the The ratio of the rms sum of harmonics to the fundamental. For midscale output code. the AD7762, it is defined as Zero Error Drift 2 2 2 2 2 + + + + The change in the actual zero error value due to a temperature THD(dB) 2 V 3 V 4 V 5 V 6 V = 20 log change of 1°C. It is expressed as a percentage of the zero error at 1 V room temperature. where: V Gain Error 1 is the rms amplitude of the fundamental. V The first transition (from 100…000 to 100…001) should occur 2, V3, V4, V5,.and V6 are the rms amplitudes of the second to the sixth harmonics. for an analog voltage 1/2 LSB above the nominal negative ful scale. The last transition (from 011…110 to 011…111) should Nonharmonic Spurious-Free Dynamic Range (SFDR) occur for an analog voltage 1 1/2 LSB below the nominal full The ratio of the rms signal amplitude to the rms value of the scale. The gain error is the deviation of the difference between peak spurious spectral component, excluding harmonics. the actual level of the last transition and the actual level of the first transition, from the difference between the ideal levels. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to Gain Error Drift the rms noise measured with the inputs shorted together. The The change in the actual gain error value due to a temperature value for dynamic range is expressed in decibels. change of 1°C. It is expressed as a percentage of the gain error at Integral Nonlinearity (INL) room temperature. The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Rev. A | Page 9 of 28 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Theory of Operation AD7762 Interface Reading Data Sharing the Parallel Bus Writing to the AD7762 Reading Status and Other Registers Clocking the AD7762 Example 1 Example 2 Driving the AD7762 Using the AD7762 Bias Resistor Selection Decoupling and Layout Recommendations Supply Decoupling Additional Decoupling Reference Voltage Filtering Differential Amplifier Components Layout Considerations Programmable FIR Filter Downloading a User-Defined Filter Example Filter Download AD7762 Registers Control Register 1—Reg 0x0001 Default Value 0x001A Control Register 2—Address 0x0002 Default Value 0x009B Status Register (Read Only) Offset Register—Address 0x0003 Non-bitmapped, Default Value 0x0000 Gain Register—Address 0x0004 Non-bitmapped, Default Value 0xA000 Overrange Register—Address 0x0005 Non-bitmapped, Default Value 0xCCCC Outline Dimensions Ordering Guide