Datasheet AD7798, AD7799 (Analog Devices) - 5

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Data Sheet AD7798/AD7799 Parameter AD7798B/AD7799B1 Unit Test Conditions/Comments
SYSTEM CALIBRATION2 Full-Scale Calibration Limit 1.05 × FS V max FS = Full-scale analog input. When VREF = AVDD, the differential input must be limited to (0.9 × VREF/gain) if the in-amp is active. Zero-Scale Calibration Limit −1.05 × FS V min Input Span 0.8 × FS V min 2.1 × FS V max POWER REQUIREMENTS7 Power Supply Voltage AVDD – GND 2.7/5.25 V min/max DVDD – GND 2.7/5.25 V min/max Power Supply Currents IDD Current 140 µA max Unbuffered mode, 110 µA typ @ AVDD = 3 V, 125 µA typ @ AVDD = 5 V 180 µA max Buffered mode, gain = 1 or 2, 130 µA typ @ AVDD = 3 V, 165 µA typ @ AVDD = 5 V 400 µA max AD7798: gain = 4 to 128, 300 µA typ @ AVDD = 3 V, 350 µA typ @ AVDD = 5 V 500 µA max AD7799: gain = 4 to 128, 380 µA typ @ AVDD = 3 V, 440 µA typ @ AVDD = 5 V IDD (Power-Down Mode) 1 µA max 1 Temperature range is –40°C to +105°C. At the 19.6 Hz and 39.2 Hz update rates, the INL, power supply rejection (PSR), common-mode rejection (CMR), and normal mode rejection (NMR) do not meet the data sheet specification if the voltage on the AIN(+) or AIN(−) pins exceeds AVDD − 1.6 V typically. When this voltage is exceeded, the INL, for example, is reduced to 18 ppm of FS typically and the PSR is reduced to 69 dB typically. Therefore, for guaranteed performance at these update rates, the absolute voltage on the analog input pins needs to be below AVDD − 1.6 V. 2 Specification is not production tested, but is supported by characterization data at initial product release. 3 Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected. 4 Recalibration at any temperature removes these errors. 5 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AVDD = 4 V, gain = 1, TA = 25°C). 6 FS[3:0] are the four bits used in the mode register to select the output word rate. 7 Digital inputs equal to DVDD or GND. Rev. B | Page 5 of 28 Document Outline Features Interface Applications Functional Block Diagram General Description Revision History Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Output Noise and Resolution Specifications AD7798 AD7799 Typical Performance Characteristics On-Chip Registers Communication Register RS2, RS1, RS0 = 0, 0, 0 Status Register RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 (AD7798)/0x88 (AD7799) Mode Register RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000A Configuration Register RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710 Data Register RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x0000(00) ID Register RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xX8 (AD7798)/0xX9 (AD7799) IO Register RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00 Offset Register RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x8000(AD7798)/0x800000 (AD7799) Full-Scale Register RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXX (AD7798)/0x5XXX00 (AD7799) ADC Circuit Information Overview Digital Interface Single-Conversion Mode Continuous-Conversion Mode Continuous Read Circuit Description Analog Input Channel Instrumentation Amplifier Bipolar/Unipolar Configuration Data Output Coding Burnout Currents Reference Reference Detect Reset AVDD Monitor Calibration Grounding and Layout Applications Information Weigh Scales Outline Dimensions Ordering Guide