Datasheet AD7787 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Low Power, 2-Channel 24-Bit Sigma-Delta ADC |
| Pages / Page | 21 / 7 — AD7787. Data Sheet. ISINK (1.6mA WITH VDD = 5V, 100. A WITH VDD = 3V). TO … |
| Revision | A |
| File Format / Size | PDF / 364 Kb |
| Document Language | English |
AD7787. Data Sheet. ISINK (1.6mA WITH VDD = 5V, 100. A WITH VDD = 3V). TO OUTPUT. 1.6V. PIN. 50pF. ISOURCE (200. A WITH VDD = 5V, 100
Model Line for this Datasheet
Text Version of Document
AD7787 Data Sheet ISINK (1.6mA WITH VDD = 5V, 100
A WITH VDD = 3V) TO OUTPUT 1.6V PIN 50pF ISOURCE (200
A WITH VDD = 5V, 100
A WITH VDD = 3V)
04477-0-002 Figure 2. Load Circuit for Timing Characterization
CS (I) t6 t1 t5 DOUT/RDY (O) MSB LSB t t7 2 t3 SCLK (I) t4 I = INPUT, O = OUTPUT
04477-0-003 Figure 3. Read Cycle Timing Diagram
CS (I) t t 8 11 SCLK (I) t9 t10 DIN (I) MSB LSB I = INPUT, O = OUTPUT
04477-0-004 Figure 4. Write Cycle Timing Diagram Rev. A | Page 6 of 20 Document Outline Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics On-Chip Registers Communications Register (RS1, RS0 = 0, 0) Status Register (RS1, RS0 = 0, 0; Power-On/Reset = 0×8C) Mode Register (RS1, RS0 = 0, 1; Power-On/Reset = 0×02) Filter Register (RS1, RS0 = 1, 0; Power-On/Reset = 0×04) Data Register (RS1, RS0 = 1, 1; Power-On/Reset = 0×000000) ADC Circuit Information Overview Noise Performance Reduced Current Modes Digital Interface Single Conversion Mode Continuous Conversion Mode Continuous Read Mode Circuit Description Analog Input Channel Bipolar/Unipolar Configuration Data Output Coding Reference Input VDD Monitor Grounding and Layout Applications Battery Monitoring Outline Dimensions Ordering Guide
A WITH VDD = 3V) TO OUTPUT 1.6V PIN 50pF ISOURCE (200
A WITH VDD = 5V, 100
A WITH VDD = 3V)
04477-0-002 Figure 2. Load Circuit for Timing Characterization
CS (I) t6 t1 t5 DOUT/RDY (O) MSB LSB t t7 2 t3 SCLK (I) t4 I = INPUT, O = OUTPUT
04477-0-003 Figure 3. Read Cycle Timing Diagram
CS (I) t t 8 11 SCLK (I) t9 t10 DIN (I) MSB LSB I = INPUT, O = OUTPUT
04477-0-004 Figure 4. Write Cycle Timing Diagram Rev. A | Page 6 of 20 Document Outline Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics On-Chip Registers Communications Register (RS1, RS0 = 0, 0) Status Register (RS1, RS0 = 0, 0; Power-On/Reset = 0×8C) Mode Register (RS1, RS0 = 0, 1; Power-On/Reset = 0×02) Filter Register (RS1, RS0 = 1, 0; Power-On/Reset = 0×04) Data Register (RS1, RS0 = 1, 1; Power-On/Reset = 0×000000) ADC Circuit Information Overview Noise Performance Reduced Current Modes Digital Interface Single Conversion Mode Continuous Conversion Mode Continuous Read Mode Circuit Description Analog Input Channel Bipolar/Unipolar Configuration Data Output Coding Reference Input VDD Monitor Grounding and Layout Applications Battery Monitoring Outline Dimensions Ordering Guide
