Datasheet AD7788, AD7789 (Analog Devices)

ManufacturerAnalog Devices
Description24-Bit, Single-Channel, Ultra Low Power, Sigma-Delta A/D Converter
Pages / Page20 / 1 — Low Power, 16-/24-Bit,. Sigma-Delta ADCs. Data Sheet. AD7788/. AD7789. …
RevisionC
File Format / SizePDF / 347 Kb
Document LanguageEnglish

Low Power, 16-/24-Bit,. Sigma-Delta ADCs. Data Sheet. AD7788/. AD7789. FEATURES. FUNCTIONAL BLOCK DIAGRAM. AD7788: 1. 6-bit resolution

Datasheet AD7788, AD7789 Analog Devices, Revision: C

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Low Power, 16-/24-Bit, Sigma-Delta ADCs Data Sheet AD7788/ AD7789 FEATURES FUNCTIONAL BLOCK DIAGRAM AD7788: 1 6-bit resolution REFIN(+) REFIN(–) GND VDD AD7789: 2 4-bit resolution AD7788/ Power AD7789 CLOCK Supply: 2.5 V to 5.25 V operation Normal: 75 µA maximum AIN(+) DOUT/RDY SERIAL Σ-Δ Power-down: 1 µA maximum DIN ADC* INTERFACE AIN(–) AND SCLK RMS noise: 1.5 µV CONTROL LOGIC CS AD7788: 1 6-bit p-p resolution AD7789: 1 9-bit p-p resolution (21.5 bits effective)
001
Integral nonlinearity: 3.5 ppm typical *AD7788: 16-BIT ADC AD7789: 24-BIT ADC
03539-
Simultaneous 50 Hz and 60 Hz rejection
Figure 1.
Internal clock oscillator VDD monitor channel 10-lead MSOP INTERFACE 3-wire serial SPI-, QSPI™-, MICROWIRE-, and DSP-compatible Schmitt trigger on SCLK APPLICATIONS Smart transmitters Battery applications Portable instrumentation Sensor measurement Temperature measurement Pressure measurement Weigh scales 4 to 20 mA loops GENERAL DESCRIPTION
The AD7788/AD7789 are low power, low noise, analog front The devices operate with a single power supply from 2.5 V to ends for low frequency measurement applications. The AD7789 5.25 V. When operating from a 3 V supply, the power dissipation contains a low noise, 24-bit, ∑-∆ analog-to-digital converter for the device is 225 µW maximum. The AD7788/AD7789 are (ADC) with one differential input. The AD7788 is a 16-bit available in a 10-lead MSOP. version of the AD7789. The devices operate from an internal clock. Therefore, the user does not have to supply a clock source to the devices. The output data rate is 16.6 Hz, which gives simultaneous 50 Hz/60 Hz rejection.
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Document Outline FEATURES INTERFACE APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS SPECIFICATIONS AD7789 AD7788 AD7788/AD7789 TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS ON-CHIP REGISTERS COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0) STATUS REGISTER (RS1, RS0 = 0, 0; Power-On/Reset = 0x88 for AD7788 and 0x8C for AD7789) MODE REGISTER (RS1, RS0 = 0, 1; Power-On/Reset = 0x02) DATA REGISTER (RS1, RS0 = 1, 1; Power-On/Reset = 0x0000 for the AD7788 and 0x000000 for the AD7789) ADC CIRCUIT INFORMATION NOISE PERFORMANCE DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read Mode CIRCUIT DESCRIPTION ANALOG INPUT CHANNEL BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING REFERENCE INPUT VDD MONITOR GROUNDING AND LAYOUT OUTLINE DIMENSIONS ORDERING GUIDE NOTES