Datasheet AD7674 (Analog Devices)
Manufacturer | Analog Devices |
Description | 18-Bit, 2.5 LSB INL, 800 kSPS, SAR ADC |
Pages / Page | 29 / 1 — 18-Bit, 2.5 LSB INL, 800 kSPS, SAR ADC. Data Sheet. AD7674. FEATURES. … |
Revision | B |
File Format / Size | PDF / 595 Kb |
Document Language | English |
18-Bit, 2.5 LSB INL, 800 kSPS, SAR ADC. Data Sheet. AD7674. FEATURES. FUNCTIONAL BLOCK DIAGRAM
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18-Bit, 2.5 LSB INL, 800 kSPS, SAR ADC Data Sheet AD7674 FEATURES FUNCTIONAL BLOCK DIAGRAM 18-bit resolution with no missing codes PDBUF REF REFGND DVDD DGND No pipeline delay (SAR architecture) AGND OVDD AVDD AD7674 Differential input range: ±VREF (VREF up to 5 V) SERIAL OGND Throughput REFBUFIN PORT 800 kSPS (warp mode) 18 IN+ SWITCHED D[17:0] 666 kSPS (normal mode) CAP DAC IN– BUSY 570 kSPS (impulse mode) PARALLEL INTERFACE RD INL: ±2.5 LSB max (±9.5 ppm of full scale) CLOCK CS Dynamic range : 103 dB typ (VREF = 5 V) PD CONTROL LOGIC AND SINAD: 100 dB typ at 2 kHz (V MODE0 REF = 5 V) CALIBRATION CIRCUITRY RESET MODE1 Parallel (18-, 16-, or 8-bit bus) and serial 5 V/3 V interface SPI/QSPI™/MICROWIRE/DSP compatible On-board reference buffer WARP IMPULSE CNVST
03083–0–001
Single 5 V supply operation
Figure 1.
Power dissipation 98 mW typ at 800 kSPS Table 1. PulSARTM Selection 78 mW typ at 500 kSPS (impulse mode) 100 kSPS to 500 kSPS to 800 kSPS to 160 µW at 1 kSPS (impulse mode) Type 250 kSPS 570 kSPS 1000 kSPS 48-lead LQFP or 48-lead LFCSP
Pseudo- AD7651, AD7650/AD7652, AD7653, Differential AD7660/ AD7664/AD7666 AD7667
Pin-to-pin compatible upgrade of AD7676, AD7678,
AD7661
and AD7679
True Bipolar AD7663 AD7665 AD7671
APPLICATIONS
True Differential AD7675 AD7676 AD7677
CT scanners
18-Bit AD7678 AD7679 AD7674
High dynamic data acquisition
Multichannel/ AD7654, AD7655 Simultaneous
Geophone and hydrophone sensors ∑-∆ replacement (low power, multichannel) PRODUCT HIGHLIGHTS Instrumentation
1. High Resolution, Fast Throughput. The AD7674 is an
Spectrum analysis
800 kSPS, charge redistribution, 18-bit, SAR ADC (no
Medical instruments
latency).
GENERAL DESCRIPTION
2. Excellent Accuracy. The AD7674 has a maximum integral The AD7674 is an 18-bit, 800 kSPS, charge redistribution, nonlinearity of 2.5 LSB with no missing 18-bit codes. successive approximation register (SAR) fully differential 3. Serial or Parallel Interface. Versatile parallel (18-, 16- or analog-to-digital converter (ADC) that operates on a single 5 V 8-bit bus) or 3-wire serial interface arrangement power supply. The device contains a high speed, 18-bit sampling compatible with both 3 V and 5 V logic. ADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports. The device is available in a 48-lead LQFP or a 48-lead LFCSP with operation specified from −40°C to +85°C.
Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION Modes of Operation Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Inputs Driver Amplifier Choice Single-to-Differential Driver Voltage Reference Power Supply POWER DISSIPATION VERSUS THROUGHPUT CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read during Conversion MICROPROCESSOR INTERFACING Serial Peripheral Interface (SPI) APPLICATIONS INFORMATION LAYOUT EVALUATING AD7674 PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE NOTES NOTES