Datasheet AD9244 (Analog Devices) - 6

ManufacturerAnalog Devices
Description14-Bit 40/65 MSPS IF Sampling Analog-To-Digital Converter
Pages / Page37 / 6 — AD9244. Test. AD9244BST-65. AD9244BST-40. Parameter. Temp. Level. Min. …
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AD9244. Test. AD9244BST-65. AD9244BST-40. Parameter. Temp. Level. Min. Typ. Max. Unit. DIGITAL SPECIFICATIONS. Table 3

AD9244 Test AD9244BST-65 AD9244BST-40 Parameter Temp Level Min Typ Max Unit DIGITAL SPECIFICATIONS Table 3

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AD9244 Test AD9244BST-65 AD9244BST-40 Parameter Temp Level Min Typ Max Min Typ Max Unit
WORST HARMONIC (SECOND or THIRD)1 fIN = 2.4 MHz 25°C V −94.5 −93.7 dBc fIN = 20 MHz 25°C V −92.8 dBc fIN = 32.5 MHz 25°C V −86.5 dBc fIN = 70 MHz 25°C V −86.1 dBc fIN = 100 MHz 25°C V −86.2 −84.5 dBc fIN = 200 MHz 25°C V −60.7 −56.6 dBc SFDR1 fIN = 2.4 MHz Full VI 78.6 82.5 dBc 25°C I 94.5 93.7 dBc fIN = 15.5 MHz (–1 dBFS) Full IV 83 dBc 25°C V 90 dBc fIN = 20 MHz Full IV 81.4 dBc 25°C I 91.8 dBc fIN = 32.5 MHz Full IV 80.0 dBc 25°C I 86.4 dBc fIN = 70 MHz Full IV 79.5 dBc 25°C V 86.1 dBc fIN = 100 MHz 25°C V 86.2 84.5 dBc fIN = 200 MHz 25°C V 60.7 56.6 dBc 1 AC specifications can be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale).
DIGITAL SPECIFICATIONS
AVDD = 5 V, DRVDD = 3 V, VREF = 2 V, external reference, unless otherwise noted.
Table 3. Test AD9244BST-65 AD9244BST-40 Parameter Temp Level Min Typ Max Min Typ Max Unit
DIGITAL INPUTS Logic 1 Voltage (OEB, DRVDD = 3 V) Full IV 2 2 V Logic 1 Voltage (OEB, DRVDD = 5 V) Full IV 3.5 3.5 V Logic 0 Voltage (OEB) Full IV 0.8 0.8 V Logic 1 Voltage (DFS, DCS) Full IV 3.5 3.5 V Logic 0 Voltage (DFS, DCS) Full IV 0.8 0.8 V Input Current Full IV 10 10 μA Input Capacitance Full V 5 5 pF CLOCK INPUT PARAMETERS Differential Input Voltage Full IV 0.4 0.4 V p-p CLK− Voltage1 Full IV 0.25 0.25 V Internal Clock Common-Mode Full V 1.6 1.6 V Single-Ended Input Voltage Logic 1 Voltage Full IV 2 2 V Logic 0 Voltage Full IV 0.8 0.8 V Input Capacitance Full V 5 5 pF Input Resistance Full V 100 100 kΩ DIGITAL OUTPUTS (DRVDD = 5 V) Logic 1 Voltage (IOH = 50 μA) Full IV 4.5 4.5 V Logic 0 Voltage (IOL = 50 μA) Full IV 0.1 0.1 V Logic 1 Voltage (IOH = 0.5 mA) Full IV 2.4 2.4 V Logic 0 Voltage (IOL = 1.6 mA) Full IV 0.4 0.4 V Rev. C | Page 5 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL APPLICATION CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW ANALOG INPUT OPERATION Single-Ended Input Configuration Differentially Driving the Analog Inputs REFERENCE OPERATION Pin-Programmable Reference Resistor-Programmable Reference Using an External Reference Digital Outputs Data Format Select (DFS) Digital Output Driver Considerations DIGITAL INPUTS AND OUTPUTS Out of Range (OTR) Digital Output Enable Function (OEB) Clock Overview Clock Input Modes Clock Input Considerations Clock Power Dissipation Clock Stabilizer (DCS) Grounding and Decoupling Analog and Digital Grounding Analog Supply Decoupling Digital Supply Decoupling Reference Decoupling CML VR EVALUATION BOARD ANALOG INPUT CONFIGURATION REFERENCE CONFIGURATION CLOCK CONFIGURATION OUTLINE DIMENSIONS ORDERING GUIDE