Datasheet AD9238 (Analog Devices) - 10

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AD9238 Table 6. 64-Lead LQFP and 64-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Description
1, 4, 13, 16 AGND Analog Ground. 2 VIN+_A Analog Input Pin (+) for Channel A. 3 VIN–_A Analog Input Pin (−) for Channel A. 5, 12, 17, 64 AVDD Analog Power Supply. 6 REFT_A Differential Reference (+) for Channel A. 7 REFB_A Differential Reference (−) for Channel A. 8 VREF Voltage Reference Input/Output. 9 SENSE Reference Mode Selection. 10 REFB_B Differential Reference (−) for Channel B. 11 REFT_B Differential Reference (+) for Channel B. 14 VIN−_B Analog Input Pin (−) for Channel B. 15 VIN+_B Analog Input Pin (+) for Channel B. 18 CLK_B Clock Input Pin for Channel B. 19 DCS Enable Duty Cycle Stabilizer (DCS) Mode (Tie High to Enable). 20 DFS Data Output Format Select Bit (Low for Offset Binary, High for Twos Complement). 21 PDWN_B Power-Down Function Selection for Channel B: Logic 0 enables Channel B. Logic 1 powers down Channel B. (Outputs static, not High-Z.) 22 OEB_B Output Enable Bit for Channel B: Logic 0 enables Data Bus B. Logic 1 sets outputs to High-Z. 23, 24, 42, 43 DNC Do Not Connect Pins. Should be left floating. 25 to 27, D0_B (LSB) to Channel B Data Output Bits. 30 to 38 D11_B (MSB) 28, 40, 53 DRGND Digital Output Ground. 29, 41, 52 DRVDD Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 μF capacitor. Recommended decoupling is 0.1 μF capacitor in parallel with 10 μF. 39 OTR_B Out-of-Range Indicator for Channel B. 44 to 51, D0_A (LSB) to Channel A Data Output Bits. 54 to 57 D11_A (MSB) 58 OTR_A Out-of-Range Indicator for Channel A. 59 OEB_A Output Enable Bit for Channel A: Logic 0 enables Data Bus A. Logic 1 sets outputs to High-Z. 60 PDWN_A Power-Down Function Selection for Channel A: Logic 0 enables Channel A. Logic 1 powers down Channel A. (Outputs static, not High-Z.) 61 MUX_SELECT Data Multiplexed Mode. (See Data Format section for how to enable; high setting disables output data multiplexed mode). 62 SHARED_REF Shared Reference Control Bit (Low for Independent Reference Mode, High for Shared Reference Mode). 63 CLK_A Clock Input Pin for Channel A. EP For the 64-Lead LFCSP only, there is an exposed pad that must connect to AGND. Rev. C | Page 9 of 48 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT AND CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING DATA FORMAT VOLTAGE REFERENCE Internal Reference Connection External Reference Operation AD9238 LQFP EVALUATION BOARD CLOCK CIRCUITRY ANALOG INPUTS REFERENCE CIRCUITRY DIGITAL CONTROL LOGIC OUTPUTS LQFP EVALUATION BOARD BILL OF MATERIALS (BOM) LQFP EVALUATION BOARD SCHEMATICS LQFP PCB LAYERS DUAL ADC LFCSP PCB POWER CONNECTOR ANALOG INPUTS OPTIONAL OPERATIONAL AMPLIFIER CLOCK VOLTAGE REFERENCE DATA OUTPUTS LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM) LFCSP PCB SCHEMATICS LFCSP PCB LAYERS THERMAL CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE