Datasheet AD7927 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 8-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP |
| Pages / Page | 29 / 6 — Data Sheet. AD7927. TIMING SPECIFICATIONS1. Table 2. Limit at TMIN, TMAX … |
| Revision | D |
| File Format / Size | PDF / 490 Kb |
| Document Language | English |
Data Sheet. AD7927. TIMING SPECIFICATIONS1. Table 2. Limit at TMIN, TMAX AD7927. Parameter. AVDD = 3 V. AVDD = 5 V. Unit. Description
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Data Sheet AD7927 TIMING SPECIFICATIONS1
AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.
Table 2. Limit at TMIN, TMAX AD7927 Parameter AVDD = 3 V AVDD = 5 V Unit Description
f 2 SCLK 10 10 kHz min 20 20 MHz max tCONVERT 16 × tSCLK 16 × tSCLK tQUIET 50 50 ns min Minimum quiet time required between CS rising edge and start of next conversion t2 10 10 ns min CS to SCLK setup time t 3 3 35 30 ns max Delay from CS until DOUT three-state disabled t 3 4 40 40 ns max Data access time after SCLK falling edge t5 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulsewidth t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulsewidth t7 10 10 ns min SCLK to DOUT valid hold time t 4 8 15/45 15/35 ns min/max SCLK falling edge to DOUT high impedance t9 10 10 ns min DIN setup time prior to SCLK falling edge t10 5 5 ns min DIN hold time after SCLK falling edge t11 20 20 ns min Sixteenth SCLK falling edge to CS high t12 1 1 μs max Power-up time from full power-down/auto shutdown mode 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V, (see Figure 2). The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means the time, quoted in the t8 timing characteristics, is the true bus relinquish time of the part and is independent of the bus loading.
200µA IOL TO OUTPUT 1.6V PIN CL 50pF
02
200µA I
0
OH
8- 08 03 Figure 2. Load Circuit for Digital Output Timing Specifications Rev. D | Page 5 of 28 Document Outline Features General Description Functional Block Diagram Product Highlights Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Control Register Sequencer Operation Shadow Register Circuit Information Converter Operation Analog Input ADC Transfer Function Handling Bipolar Input Signals Typical Connection Diagram Analog Input Selection Digital Inputs VDRIVE The Reference Modes of Operation Normal Mode (PM1 = PM0 = 1) Full Shutdown (PM1 = 1, PM0 = 0) Auto Shutdown (PM1 = 0, PM0 = 1) Powering Up the AD7927 Power vs. Throughput Rate Serial Interface Writing Between Conversions Microprocessor Interfacing AD7927 to TMS320C541 AD7927 to ADSP-21xx AD7927 to DSP563xx Application Hints Grounding and Layout Outline Dimensions Ordering Guide Automotive Products
Data Sheet AD7927 TIMING SPECIFICATIONS1
AVDD = 2.7 V to 5.25 V, VDRIVE ≤ AVDD, REFIN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.
Table 2. Limit at TMIN, TMAX AD7927 Parameter AVDD = 3 V AVDD = 5 V Unit Description
f 2 SCLK 10 10 kHz min 20 20 MHz max tCONVERT 16 × tSCLK 16 × tSCLK tQUIET 50 50 ns min Minimum quiet time required between CS rising edge and start of next conversion t2 10 10 ns min CS to SCLK setup time t 3 3 35 30 ns max Delay from CS until DOUT three-state disabled t 3 4 40 40 ns max Data access time after SCLK falling edge t5 0.4 × tSCLK 0.4 × tSCLK ns min SCLK low pulsewidth t6 0.4 × tSCLK 0.4 × tSCLK ns min SCLK high pulsewidth t7 10 10 ns min SCLK to DOUT valid hold time t 4 8 15/45 15/35 ns min/max SCLK falling edge to DOUT high impedance t9 10 10 ns min DIN setup time prior to SCLK falling edge t10 5 5 ns min DIN hold time after SCLK falling edge t11 20 20 ns min Sixteenth SCLK falling edge to CS high t12 1 1 μs max Power-up time from full power-down/auto shutdown mode 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of AVDD) and timed from a voltage level of 1.6 V, (see Figure 2). The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means the time, quoted in the t8 timing characteristics, is the true bus relinquish time of the part and is independent of the bus loading.
200µA IOL TO OUTPUT 1.6V PIN CL 50pF
02
200µA I
0
OH
8- 08 03 Figure 2. Load Circuit for Digital Output Timing Specifications Rev. D | Page 5 of 28 Document Outline Features General Description Functional Block Diagram Product Highlights Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Control Register Sequencer Operation Shadow Register Circuit Information Converter Operation Analog Input ADC Transfer Function Handling Bipolar Input Signals Typical Connection Diagram Analog Input Selection Digital Inputs VDRIVE The Reference Modes of Operation Normal Mode (PM1 = PM0 = 1) Full Shutdown (PM1 = 1, PM0 = 0) Auto Shutdown (PM1 = 0, PM0 = 1) Powering Up the AD7927 Power vs. Throughput Rate Serial Interface Writing Between Conversions Microprocessor Interfacing AD7927 to TMS320C541 AD7927 to ADSP-21xx AD7927 to DSP563xx Application Hints Grounding and Layout Outline Dimensions Ordering Guide Automotive Products
