Datasheet AD7910, AD7920 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | 250 kSPS, 12- Bit ADC in 6 Lead SC70 |
| Pages / Page | 24 / 7 — AD7910/AD7920. TIMING EXAMPLES. TIMING EXAMPLE 2. TIMING EXAMPLE 1. … |
| Revision | C |
| File Format / Size | PDF / 498 Kb |
| Document Language | English |
AD7910/AD7920. TIMING EXAMPLES. TIMING EXAMPLE 2. TIMING EXAMPLE 1. tCONVERT. SCLK. tQUIET. SDATA. ZERO. DB11. DB10. DB2. DB1. DB0. THREE-
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AD7910/AD7920 TIMING EXAMPLES
Figure 3 and Figure 4 show some of the timing parameters from
TIMING EXAMPLE 2
Table 3. The AD7920 can also operate with slower clock frequencies.
TIMING EXAMPLE 1
From Figure 4, having fSCLK = 3.4 MHz and a throughput rate of 150 kSPS gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 6.66 μs. From Figure 4, having fSCLK = 5 MHz and a throughput rate of With t2 = 10 ns min, this leaves tACQ to be 2.97 μs. This 2.97 μs 250 kSPS gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 4 μs. satisfies the requirement of 250 ns for tACQ. From Figure 4, tACQ With t2 = 10 ns min, this leaves tACQ to be 1.49 μs. This 1.49 μs comprises 2.5(1/fSCLK) + t8 + tQUIET, t8 = 36 ns max. This allows a satisfies the requirement of 250 ns for tACQ. From Figure 4, tACQ value of 2.19 μs for tQUIET, satisfying the minimum requirement comprises 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 36 ns max. This of 50 ns. As in this example and with other slower clock values, allows a value of 954 ns for tQUIET, satisfying the minimum the signal may already be acquired before the conversion is requirement of 50 ns. complete, but it is still necessary to leave 50 ns minimum tQUIET between conversions. In this example, the signal should be fully acquired at approximately Point C in Figure 4.
t1 CS tCONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 15 16 t5 t8 t3 t4 t7 tQUIET SDATA Z ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0 THREE- THREE-STATE STATE 4 LEADING ZEROS
02976-003 Figure 3. AD7920 Serial Interface Timing Diagram
CS tCONVERT t2 B C SCLK 1 2 3 4 5 13 14 15 16 t8 tQUIET 12.5(1/f t SCLK) ACQ 1/THROUGHPUT
02976-004 Figure 4. Serial Interface Timing Example Rev. C | Page 7 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS AD7910 AD7920 TIMING SPECIFICATIONS TIMING EXAMPLES TIMING EXAMPLE 1 TIMING EXAMPLE 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7910/AD7920 TO TMS320C541 INTERFACE AD7910/AD7920 TO ADSP-218x AD7910/AD7920 TO DSP563xx INTERFACE APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
AD7910/AD7920 TIMING EXAMPLES
Figure 3 and Figure 4 show some of the timing parameters from
TIMING EXAMPLE 2
Table 3. The AD7920 can also operate with slower clock frequencies.
TIMING EXAMPLE 1
From Figure 4, having fSCLK = 3.4 MHz and a throughput rate of 150 kSPS gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 6.66 μs. From Figure 4, having fSCLK = 5 MHz and a throughput rate of With t2 = 10 ns min, this leaves tACQ to be 2.97 μs. This 2.97 μs 250 kSPS gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 4 μs. satisfies the requirement of 250 ns for tACQ. From Figure 4, tACQ With t2 = 10 ns min, this leaves tACQ to be 1.49 μs. This 1.49 μs comprises 2.5(1/fSCLK) + t8 + tQUIET, t8 = 36 ns max. This allows a satisfies the requirement of 250 ns for tACQ. From Figure 4, tACQ value of 2.19 μs for tQUIET, satisfying the minimum requirement comprises 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 36 ns max. This of 50 ns. As in this example and with other slower clock values, allows a value of 954 ns for tQUIET, satisfying the minimum the signal may already be acquired before the conversion is requirement of 50 ns. complete, but it is still necessary to leave 50 ns minimum tQUIET between conversions. In this example, the signal should be fully acquired at approximately Point C in Figure 4.
t1 CS tCONVERT t2 t6 B SCLK 1 2 3 4 5 13 14 15 16 t5 t8 t3 t4 t7 tQUIET SDATA Z ZERO ZERO ZERO DB11 DB10 DB2 DB1 DB0 THREE- THREE-STATE STATE 4 LEADING ZEROS
02976-003 Figure 3. AD7920 Serial Interface Timing Diagram
CS tCONVERT t2 B C SCLK 1 2 3 4 5 13 14 15 16 t8 tQUIET 12.5(1/f t SCLK) ACQ 1/THROUGHPUT
02976-004 Figure 4. Serial Interface Timing Example Rev. C | Page 7 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS AD7910 AD7920 TIMING SPECIFICATIONS TIMING EXAMPLES TIMING EXAMPLE 1 TIMING EXAMPLE 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT DIGITAL INPUTS MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER VS. THROUGHPUT RATE SERIAL INTERFACE MICROPROCESSOR INTERFACING AD7910/AD7920 TO TMS320C541 INTERFACE AD7910/AD7920 TO ADSP-218x AD7910/AD7920 TO DSP563xx INTERFACE APPLICATION HINTS GROUNDING AND LAYOUT EVALUATING PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
