Datasheet AD7738 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 8-Channel, 8.5 kHz, 24-Bit Sigma-Delta A/D Converter |
| Pages / Page | 29 / 10 — AD7738. OUTPUT NOISE AND RESOLUTION SPECIFICATION. CHOPPING ENABLED. … |
| File Format / Size | PDF / 422 Kb |
| Document Language | English |
AD7738. OUTPUT NOISE AND RESOLUTION SPECIFICATION. CHOPPING ENABLED. Table I. Typical Output RMS Noise in
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AD7738 OUTPUT NOISE AND RESOLUTION SPECIFICATION
The AD7738 can be operated with chopping enabled or disabled, allowing the ADC to be programmed either to optimize the throughput rate and channel switching time or to optimize offset drift performance. Noise tables for these two primary modes of operation are outlined below for a selection of output rates and settling times.
CHOPPING ENABLED
The first mode, in which the AD7738 is configured with chopping enabled (CHOP = 1), provides very low noise numbers with lower output rates. Tables I to III show the –3 dB frequencies and typical performance versus channel conversion time or equivalent output data rate, respectively. Table I shows the typical output rms noise. Table II shows the typical effective resolution based on the rms noise. Table III shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a six-sigma limit. The peak-to-peak resolutions are not calculated based on rms noise, but on peak-to-peak noise. These typical numbers are generated from 4096 data samples acquired in Continuous Conversion mode with an analog input voltage set to 0 V and MCLK = 6.144 MHz. The Conversion Time is selected via the Channel Conversion Time register.
Table I. Typical Output RMS Noise in V vs. Conversion Time and Input Range with Chopping Enabled Conversion Conversion Output –3 dB Input Range Time Time Data Rate Frequency FW Register ( s) (Hz) (Hz) 2.5 V, +2.5 V 1.25 V, +1.25 V, 625 mV, +625 mV
127 FFh 2686 372 194 1.8 1.1 46 AEh 999 1001 521 3.0 1.8 17 91h 395 2534 1317 5.1 3.0 8 88h 207 4826 2510 8.1 4.5 4 84h 124 8074 4198 9.3 5.3 2 82h 82 12166 6326 17.0 10.6
Table II. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled Conversion Conversion Output –3 dB Input Range Time Time Data Rate Frequency FW Register ( s) (Hz) (Hz) 2.5 V +2.5 V 1.25 V +1.25 V 625 mV +625 mV
127 FFh 2686 372 194 21.4 20.4 21.1 20.1 20.1 19.1 46 AEh 999 1001 521 20.6 19.6 20.4 19.4 19.4 18.4 17 91h 395 2534 1317 19.9 18.9 19.6 18.6 18.6 17.6 8 88h 207 4826 2510 19.2 18.2 19.0 18.0 18.0 17.0 4 84h 124 8074 4198 19.0 18.0 18.8 17.8 17.8 16.8 2 82h 82 12166 6326 18.1 17.1 17.8 16.8 16.8 15.8
Table III. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled Conversion Conversion Output –3 dB Input Range Time Time Data Rate Frequency FW Register ( s) (Hz) (Hz) 2.5 V +2.5 V 1.25 V +1.25 V 625 mV +625 mV
127 FFh 2686 372 194 18.4 17.4 18.2 17.2 17.2 16.2 46 AEh 999 1001 521 17.8 16.8 17.5 16.5 16.5 15.5 17 91h 395 2534 1317 16.8 15.8 16.7 15.7 15.7 14.7 8 88h 207 4826 2510 16.5 15.5 16.2 15.2 15.2 14.2 4 84h 124 8074 4198 16.0 15.0 16.0 15.0 15.0 14.0 2 82h 82 12166 6326 15.0 14.0 15.0 14.0 14.0 13.0 REV. 0 –9– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTION PIN FUNCTION DESCRIPTION (continued) OUTPUT NOISE AND RESOLUTION SPECIFICATION CHOPPING ENABLED CHOPPING DISABLED Typical Performance Characteristics REGISTER DESCRIPTION Communications Register I/O Port Register Revision Register Test Register ADC Status Register Checksum Register ADC Zero Scale Calibration Register ADC Full-Scale Register Channel Data Registers Channel Zero-Scale Calibration Registers Channel Full-Scale Calibration Registers Channel Status Registers Channel Setup Registers Channel Conversion Time Registers Mode Register DIGITAL INTERFACE DESCRIPTION Hardware Reset Access the AD7738 Registers Single Conversion and Reading Data Dump Mode Continuous Conversion Mode Continuous Read (Continuous Conversion) Mode CIRCUIT DESCRIPTION Analog Front End Sigma-Delta ADC Chopping Multiplexer, Conversion, and Data Output Timing Frequency Response Analog Inputs Voltage Range Analog Inputs Extended Voltage Range Voltage Reference Inputs Reference Detect I/O Port CALIBRATION ADC Zero-Scale Self-Calibration Per Channel System Calibration OUTLINE DIMENSIONS
The AD7738 can be operated with chopping enabled or disabled, allowing the ADC to be programmed either to optimize the throughput rate and channel switching time or to optimize offset drift performance. Noise tables for these two primary modes of operation are outlined below for a selection of output rates and settling times.
CHOPPING ENABLED
The first mode, in which the AD7738 is configured with chopping enabled (CHOP = 1), provides very low noise numbers with lower output rates. Tables I to III show the –3 dB frequencies and typical performance versus channel conversion time or equivalent output data rate, respectively. Table I shows the typical output rms noise. Table II shows the typical effective resolution based on the rms noise. Table III shows the typical output peak-to-peak resolution, representing values for which there will be no code flicker within a six-sigma limit. The peak-to-peak resolutions are not calculated based on rms noise, but on peak-to-peak noise. These typical numbers are generated from 4096 data samples acquired in Continuous Conversion mode with an analog input voltage set to 0 V and MCLK = 6.144 MHz. The Conversion Time is selected via the Channel Conversion Time register.
Table I. Typical Output RMS Noise in V vs. Conversion Time and Input Range with Chopping Enabled Conversion Conversion Output –3 dB Input Range Time Time Data Rate Frequency FW Register ( s) (Hz) (Hz) 2.5 V, +2.5 V 1.25 V, +1.25 V, 625 mV, +625 mV
127 FFh 2686 372 194 1.8 1.1 46 AEh 999 1001 521 3.0 1.8 17 91h 395 2534 1317 5.1 3.0 8 88h 207 4826 2510 8.1 4.5 4 84h 124 8074 4198 9.3 5.3 2 82h 82 12166 6326 17.0 10.6
Table II. Typical Effective Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled Conversion Conversion Output –3 dB Input Range Time Time Data Rate Frequency FW Register ( s) (Hz) (Hz) 2.5 V +2.5 V 1.25 V +1.25 V 625 mV +625 mV
127 FFh 2686 372 194 21.4 20.4 21.1 20.1 20.1 19.1 46 AEh 999 1001 521 20.6 19.6 20.4 19.4 19.4 18.4 17 91h 395 2534 1317 19.9 18.9 19.6 18.6 18.6 17.6 8 88h 207 4826 2510 19.2 18.2 19.0 18.0 18.0 17.0 4 84h 124 8074 4198 19.0 18.0 18.8 17.8 17.8 16.8 2 82h 82 12166 6326 18.1 17.1 17.8 16.8 16.8 15.8
Table III. Typical Peak-to-Peak Resolution in Bits vs. Conversion Time and Input Range with Chopping Enabled Conversion Conversion Output –3 dB Input Range Time Time Data Rate Frequency FW Register ( s) (Hz) (Hz) 2.5 V +2.5 V 1.25 V +1.25 V 625 mV +625 mV
127 FFh 2686 372 194 18.4 17.4 18.2 17.2 17.2 16.2 46 AEh 999 1001 521 17.8 16.8 17.5 16.5 16.5 15.5 17 91h 395 2534 1317 16.8 15.8 16.7 15.7 15.7 14.7 8 88h 207 4826 2510 16.5 15.5 16.2 15.2 15.2 14.2 4 84h 124 8074 4198 16.0 15.0 16.0 15.0 15.0 14.0 2 82h 82 12166 6326 15.0 14.0 15.0 14.0 14.0 13.0 REV. 0 –9– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTION PIN FUNCTION DESCRIPTION (continued) OUTPUT NOISE AND RESOLUTION SPECIFICATION CHOPPING ENABLED CHOPPING DISABLED Typical Performance Characteristics REGISTER DESCRIPTION Communications Register I/O Port Register Revision Register Test Register ADC Status Register Checksum Register ADC Zero Scale Calibration Register ADC Full-Scale Register Channel Data Registers Channel Zero-Scale Calibration Registers Channel Full-Scale Calibration Registers Channel Status Registers Channel Setup Registers Channel Conversion Time Registers Mode Register DIGITAL INTERFACE DESCRIPTION Hardware Reset Access the AD7738 Registers Single Conversion and Reading Data Dump Mode Continuous Conversion Mode Continuous Read (Continuous Conversion) Mode CIRCUIT DESCRIPTION Analog Front End Sigma-Delta ADC Chopping Multiplexer, Conversion, and Data Output Timing Frequency Response Analog Inputs Voltage Range Analog Inputs Extended Voltage Range Voltage Reference Inputs Reference Detect I/O Port CALIBRATION ADC Zero-Scale Self-Calibration Per Channel System Calibration OUTLINE DIMENSIONS
