link to page 14 link to page 14 link to page 14 AD7482PIN CONFIGURATION AND FUNCTION DESCRIPTIONST SE1E2NDNDDDDDNVLIPESETAGAGAVCMOMORCOD12D11D10D948 47 46 45 44 43 42 41 40 39 38 37AV136DDD8PIN 1C2IDENTIFIERBIAS35 D7AGND334 D6AGND433 D5AV5DD32 VDRIVEAD7482AGND631 DGNDTOP VIEWVIN7(Not to Scale)30 DGNDREFOUT829 DVDDREFIN928 D4REFSEL 1027 D311AGND26 D2AGND 1225 D113 14 15 16 17 18 19 20 21 22 23 24YDDNDNDBYCSRDR1R2D0 002 TITENAPAVAGAGSWRBUS 02638- Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No.Mnemonic Description 1, 5, 13, 46 AVDD Positive Power Supply for Analog Circuitry. 2 CBIAS Decoupling Pin for Internal Bias Voltage. A 1 nF capacitor should be placed between this pin and AGND. 3, 4, 6, 11, 12, AGND Power Supply Ground for Analog Circuitry. 14, 15, 47, 48 7 VIN Analog Input. Single ended analog input channel. 8 REFOUT Reference Output. REFOUT connects to the output of the internal 2.5 V reference buffer. A 470 nF capacitor must be placed between this pin and AGND. 9 REFIN Reference Input. A 470 nF capacitor must be placed between this pin and AGND. When using an external voltage reference source, the reference voltage should be applied to this pin. 10 REFSEL Reference Decoupling Pin. When using the internal reference, a 1 nF capacitor must be connected from this pin to AGND. When using an external reference source, this pin should be connected directly to AGND. 16 STBY Standby Logic Input. When this pin is logic high, the device is placed in standby mode. See the Power Saving section for further details. 17 NAP Nap Logic Input. When this pin is logic high, the device is placed in a very low power mode. See the Power Saving section for further details. 18 CS Chip Select Logic Input. This pin is used in conjunction with RD to access the conversion result. The data bus is brought out of three-state and the current contents of the output register driven onto the data lines following the falling edge of both CS and RD. CS is also used in conjunction with WRITE to perform a write to the offset register. CS can be hardwired permanently low. 19 RD Read Logic Input. Used in conjunction with CS to access the conversion result. 20 WRITE Write Logic Input. Used in conjunction with CS to write data to the offset register. When the desired offset word has been placed on the data bus, the WRITE line should be pulsed high. It is the falling edge of this pulse that latches the word into the offset register. 21 BUSY Busy Logic Output. This pin indicates the status of the conversion process. The BUSY signal goes low after the falling edge of CONVST and stays low for the duration of the conversion. In Parallel Mode 1, the BUSY signal returns high when the conversion result has been latched into the output register. In Parallel Mode 2, the BUSY signal returns high as soon as the conversion has been completed, but the conversion result does not get latched into the output register until the falling edge of the next CONVST pulse. 22, 23 R1, R2 No Connect. These pins should be pulled to ground via 100 kΩ resistors. 24 to 28, D0 to D11 Data I/O Bits. D11 is MSB. These are three-state pins that are controlled by CS, RD, and WRITE. The operating 33 to 39 voltage level for these pins is determined by the VDRIVE input. 29 DVDD Positive Power Supply for Digital Circuitry. Rev. B | Page 7 of 20 Document Outline Features Functional Block Diagram General Description Revision History Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Circuit Description Converter Operation Analog Input ADC Transfer Function Power Saving Offset/Overrange Parallel Interface Reading Data from the AD7482 Writing to the AD7482 Driving the CONVST Pin Typical Connection Board Layout and Grounding Outline Dimensions Ordering Guide