Datasheet AD7783 (Analog Devices) - 5

AD7783 TIMING CHARACTERISTICS1, 2 (VDD = 2.7 V to 3.6 V or VDD = 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz; Input Logic 0 = 0 V, Logic 1 = VDD, unless otherwise noted.) Limit at TMIN, TMAX Parameter (B Version) Unit Conditions/Comments
t1 30.5176 ms typ Crystal Oscillator Period tADC 50.54 ms typ 19.79 Hz Update Rate t2 0 ns min CS Falling Edge to DOUT Active 60 ns max VDD = 4.75 V to 5.25 V 80 ns max VDD = 2.7 V to 3.6 V t3 2 ¥ tADC ns typ Channel Settling Time t 3 4 0 ns min SCLK Active Edge to Data Valid Delay4 60 ns max VDD = 4.75 V to 5.25 V 80 ns max VDD = 2.7 V to 3.6 V t 5 7 10 ns min Bus Relinquish Time after CS Inactive Edge 80 ns max t8 0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time t9 10 ns min SCLK Inactive to DOUT High 80 ns max Slave Mode Timing t5 100 ns min SCLK High Pulse Width t6 100 ns min SCLK Low Pulse Width Master Mode Timing t5 t1/2 ms typ SCLK High Pulse Width t6 t1/2 ms typ SCLK Low Pulse Width t10 t1/2 ms min DOUT Low to First SCLK Active Edge4 3t1/2 ms max NOTES 1Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. 2See Figure 2. 3These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VOL or VOH limits. 4SCLK active edge is falling edge of SCLK. 5These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means the times quoted in the timing characteristics are the true bus relin- quish times of the part and as such are independent of external bus loading capacitances.
ISINK (1.6mA WITH VDD = 5V 100
␮
A WITH VDD = 3V) TO OUTPUT 1.6V PIN 50pF ISOURCE ( 200
␮
A WITH VDD = 5V 100
␮
A WITH VDD = 3V)
Figure 1. Load Circuit for Timing Characterization –4– REV. C Document Outline FEATURES INTERFACE POWER ON-CHIP FUNCTIONS APPLICATIONS FUNCTIONAL BLOCK DIAGRAM BASIC CONNECTION DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics ADC CIRCUIT INFORMATION Overview NOISE PERFORMANCE DIGITAL INTERFACE MASTER MODE (MODE = 0) SLAVE MODE (MODE = 1) CIRCUIT DESCRIPTION Analog Input Channel Programmable Gain Amplifier Bipolar Configuration/Output Coding Excitation Currents Crystal Oscillator Reference Input Grounding and Layout OUTLINE DIMENSIONS Revision History