Datasheet AD7675 (Analog Devices) - 4

AD7675 TIMING SPECIFICATIONS (–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) Symbol Min Typ Max Unit
Refer to Figures 11 and 12 Convert Pulsewidth t1 5 ns Time Between Conversions t2 10 µs CNVST LOW to BUSY HIGH Delay t3 30 ns BUSY HIGH All Modes Except in Master Serial Read t4 1.25 µs After Convert Mode Aperture Delay t5 2 ns End of Conversion to BUSY LOW Delay t6 10 ns Conversion Time t7 1.25 µs Acquisition Time t8 8.75 µs RESET Pulsewidth t9 10 ns Refer to Figures 13, 14, and 15 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay t10 1.25 µs DATA Valid to BUSY LOW Delay t11 45 ns Bus Access Request to DATA Valid t12 40 ns Bus Relinquish Time t13 5 15 ns Refer to Figures 16 and 17 (Master Serial Interface Modes)1 CS LOW to SYNC Valid Delay t14 10 ns CS LOW to Internal SCLK Valid Delay t15 10 ns CS LOW to SDOUT Delay t16 10 ns CNVST LOW to SYNC Delay t17 525 ns SYNC Asserted to SCLK First Edge Delay2 t18 3 ns Internal SCLK Period2 t19 25 40 ns Internal SCLK HIGH2 t20 12 ns Internal SCLK LOW2 t21 7 ns SDOUT Valid Setup Time2 t22 4 ns SDOUT Valid Hold Time2 t23 2 ns SCLK Last Edge to SYNC Delay2 t24 3 ns CS HIGH to SYNC HI-Z t25 10 ns CS HIGH to Internal SCLK HI-Z t26 10 ns CS HIGH to SDOUT HI-Z t27 10 ns BUSY HIGH in Master Serial Read After Convert2 t28 See Table I µs CNVST LOW to SYNC Asserted Delay t29 1.25 µs SYNC Deasserted to BUSY LOW Delay t30 25 ns Refer to Figures 18 and 19 (Slave Serial Interface Modes) External SCLK Setup Time t31 5 ns External SCLK Active Edge to SDOUT Delay t32 3 18 ns SDIN Setup Time t33 5 ns SDIN Hold Time t34 5 ns External SCLK Period t35 25 ns External SCLK HIGH t36 10 ns External SCLK LOW t37 10 ns NOTES 1In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 2In serial master read during convert mode. See Table I for serial master read after convert mode. Specifications subject to change without notice. REV. A –3– Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PulSAR Selection GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS Table I. Serial Clock Timings in Master Read after Convert ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION DEFINITION OF SPECIFICATIONS INTEGRAL NONLINEARITY ERROR (INL) DIFFERENTIAL NONLINEARITY ERROR (DNL) +FULL-SCALE ERROR –FULL-SCALE ERROR BIPOLAR ZERO ERROR SPURIOUS FREE DYNAMIC RANGE (SFDR) EFFECTIVE NUMBER OF BITS (ENOB) TOTAL HARMONIC DISTORTION (THD) SIGNAL-TO-NOISE RATIO (SNR) SIGNAL-TO-(NOISE + DISTORTION) RATIO (S/[N+D]) APERTURE DELAY TRANSIENT RESPONSE Typical Performance Characteristics CIRCUIT INFORMATION CONVERTER OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Inputs Single to Differential Driver Driver Amplifier Choice Voltage Reference Input Power Supply POWER DISSIPATION CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read During Conversion MICROPROCESSOR INTERFACING SPI Interface (MC68HC11) ADSP-21065L in Master Serial Interface APPLICATION HINTS Layout Evaluating the AD7675 Performance OUTLINE DIMENSIONS Revision History