Datasheet AD7671 (Analog Devices) - 8

AD7671 PIN FUNCTION DESCRIPTION (continued) Pin No. Mnemonic Type Description
21 D[8] DO When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus. or SDOUT When SER/PAR is HIGH, this output, part of the Serial Port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7671 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. In Serial Mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In Serial Mode, when EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge. 22 D[9] DI/O When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus. or SCLK When SER/PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. 23 D[10] DO When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus. or SYNC When SER/PAR is HIGH, this output, part of the Serial Port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. 24 D[11] DO When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus. or RDERROR When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is used as an incomplete read error flag. In Slave Mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH. 25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. 29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data-ready clock signal. 30 DGND P Must Be Tied to Digital Ground. 31 RD DI Read Data. When CS and RD are both LOW, the Interface Parallel or Serial Output Bus is enabled. 32 CS DI Chip Select. When CS and RD are both LOW, the Interface Parallel or Serial Output Bus is enabled. CS is also used to gate the external serial clock. 33 RESET DI Reset Input. When set to a logic HIGH, reset the AD7671. Current conversion, if any, is aborted. If not used, this pin could be tied to DGND. 34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. 35 CNVST DI Start Conversion. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. In Impulse Mode (IMPULSE HIGH and WARP LOW), if CNVST is held LOW when the acquisition phase (t8) is complete, the internal sample-and-hold is put into the hold state and a conversion is immediately started. 36 AGND P Must Be Tied to Analog Ground. 37 REF AI Reference Input Voltage. 38 REFGND AI Reference Input Analog Ground. 39 INGND P Analog Input Ground. 40, 41, INA, INB, AI Analog Inputs. Refer to Table I for input range configuration. 42, 43 INC, IND NOTES AI = Analog Input DI = Digital Input DI/O = Bidirectional Digital DO = Digital Output P = Power Paddle connected to AGND for the LFCSP (CP-48-1). This connection is not required to meet the electrical performances. REV. C –7– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PulSAR Selection PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDERING GUIDE PIN FUNCTION DESCRIPTION DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Differential Nonlinearity Error (DNL) Full-Scale Error Bipolar Zero Error Unipolar Zero Error Spurious-Free Dynamic Range (SFDR) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Signal-to-(Noise + Distortion) Ratio (S/[N+D]) Aperture Delay Transient Response Typical Performance Characteristics CIRCUIT INFORMATION CONVERTER OPERATION Modes of Operation Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Inputs Driver Amplifier Choice Voltage Reference Input Scaler Reference Input (Bipolar Input Ranges) Power Supply POWER DISSIPATION CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE SLAVE SERIAL INTERFACE External Clock MASTER SERIAL INTERFACE Internal Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read during Conversion MICROPROCESSOR INTERFACING SPI Interface (MC68HC11) ADSP-21065L in Master Serial Interface APPLICATION HINTS Layout Evaluating the AD7671 Performance OUTLINE DIMENSIONS Revision History