Datasheet AD7665 (Analog Devices) - 20

AD7665 EXT/INT = 1 INVSCLK = 0 RD = 0 CS BUSY t35 t36 t37 SCLK 1 2 3 14 15 16 17 18 t31 t32 SDOUT X D15 D14 D13 D1 D0 X15 X14 t16 t34 SDIN X15 X14 X13 X1 X0 Y15 Y14 t33
Figure 19. Slave Serial Data Timing for Reading (Read after Convert) In Read-during-Conversion Mode, the serial clock and data toggle 16 clock pulses and is valid on both the rising and falling edge at appropriate instants, which minimizes potential feedthrough of the clock. between digital activity and the critical conversion decisions. Among the advantages of this method, the conversion performance In Read-after-Conversion Mode, it should be noted that unlike is not degraded because there are no voltage transients on the in other modes, the signal BUSY returns LOW after the 16 data digital interface during the conversion process. bits are pulsed out and not at the end of the conversion phase, Another advantage is to be able to read the data at any speed up which results in a longer BUSY width. to 40 MHz, which accommodates both slow digital host interface and the fastest serial reading.
SLAVE SERIAL INTERFACE External Clock
Finally, in this mode only, the AD7665 provides a “daisy-chain” The AD7665 is configured to accept an externally supplied serial feature using the RDC/SDIN input pin for cascading multiple data clock on the SCLK pin when the EXT/INT pin is held converters together. This feature is useful for reducing component HIGH. In this mode, several methods can be used to read the count and wiring connections when desired as, for instance, in data. The external serial clock is gated by CS and the data are isolated multiconverter applications. output when both CS and RD are LOW. Thus, depending on CS, An example of the concatenation of two devices is shown in the data can be read after each conversion or during the follow- Figure 20. Simultaneous sampling is possible by using a com- ing conversion. The external clock can be either a continuous or mon CNVST signal. It should be noted that the RDC/SDIN discontinuous clock. A discontinuous clock can be either normally input is latched on the opposite edge of SCLK of the one used HIGH or normally LOW when inactive. Figures 19 and 21 show to shift out the data on SDOUT. Therefore, the MSB of the the detailed timing diagrams of these methods. “upstream” converter just follows the LSB of the “downstream” While the AD7665 is performing a bit decision, it is important converter on the next SCLK cycle. that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. This is particu-
BUSY OUT
larly important during the second half of the conversion phase because the AD7665 provides error correction circuitry that can
BUSY BUSY
correct for an improper bit decision made during the first half of
AD7665 AD7665
the conversion phase. For this reason, it is recommended that
#2 #1
when an external clock is being provided, it is a discontinuous clock
(UPSTREAM) (DOWNSTREAM) DATA
that is toggling only when BUSY is LOW or, more importantly,
RDC/SDIN SDOUT RDC/SDIN SDOUT OUT
that does not transition during the latter half of BUSY HIGH.
CNVST CNVST External Discontinuous Clock Data Read after Conversion CS CS
Though the maximum throughput cannot be achieved using this
SCLK SCLK
mode, it is the most recommended of the serial slave modes. Figure 19 shows the detailed timing diagrams of this method. After a conversion is complete, indicated by BUSY returning
SCLK IN
LOW, the result of this conversion can be read while both CS
CS IN CNVST IN
and RD are LOW. The data is shifted out, MSB first, with Figure 20. Two AD7665s in a Daisy-Chain Configuration REV. C –19–