Datasheet AD7665 (Analog Devices) - 7

AD7665 PIN FUNCTION DESCRIPTION Pin No. Mnemonic Type Description
1 AGND P Analog Power Ground Pin. 2 AVDD P Input Analog Power Pin. Nominally 5 V. 3, 44–48 NC No Connect. 4 BYTESWAP Parallel Mode Selection (8/16 Bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. 5 OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register. 6 WARP DI Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion rate. 7 IMPULSE DI Mode Selection. When HIGH and WARP LOW, this input selects a reduced Power Mode. In this mode, the power dissipation is approximately proportional to the sampling rate. 8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the Serial Interface Mode is selected and some bits of the data bus are used as a Serial Port. 9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. 11, 12 D[2:3] or DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data Output Bus. DIVSCLK[0:1] When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the Serial Master Read after Convert Mode. These inputs, part of the Serial Port, are used to slow down, if desired, the internal serial clock that clocks the data output. In the other serial modes, these pins are high impedance outputs. 13 D[4] DI/O When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus. or EXT/INT When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input for choosing the internal or an external data clock, called respectively, Master and Slave Modes. With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input and the external clock is gated by CS. 14 D[5] DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus. or INVSYNC When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. 15 D[6] DI/O When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus. or INVSCLK When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal. It is active in both master and slave mode. 16 D[7] DI/O When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus. or RDC/SDIN When SER/PAR is HIGH, this input, part of the Serial Port, is used as either an external data input or a read mode selection input, depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the Read Mode. When RDC/SDIN is HIGH, the previous data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. 17 OGND P Input/Output Interface Digital Power Ground. 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (5 V or 3 V). 19 DVDD P Digital Power. Nominally at 5 V. 20 DGND P Digital Power Ground. –6– REV. C