Datasheet AD7663 (Analog Devices) - 4

AD7663 Parameter Conditions Min Typ Max Unit
TEMPERATURE RANGE8 Specified Performance TMIN to TMAX –40 +85 °C NOTES 1LSB means least significant bit. With the ±5 V input range, one LSB is 152.588 µV. 2See Definition of Specifications section. These specifications do not include the error contribution from the external reference. 3All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 4The max should be the minimum of 5.25 V and DVDD + 0.3 V. 5Tested in Parallel Reading Mode. 6Tested with the 0 V to 5 V range and VIN – VINGND = 0 V. See Power Dissipation section. 7With OVDD below DVDD + 0.3 V and all digital inputs forced to DVDD or DGND, respectively. 8Contact factory for extended temperature range. Specifications subject to change without notice.
Table I. Analog Input Configuration Input Voltage Input Range IND(4R) INC(4R) INB(2R) INA(R) Impedance1
±4 REF2 VIN INGND INGND REF 5.85 kW ±2 REF VIN VIN INGND REF 3.41 kW ±REF VIN VIN VIN REF 2.56 kW 0 V to 4 REF VIN VIN INGND INGND 3.41 kW 0 V to 2 REF VIN VIN VIN INGND 2.56 kW 0 V to REF VIN VIN VIN VIN Note 3 NOTES 1Typical analog input impedance. 2With REF = 3 V, in this range, the input should be limited to –11 V to +12 V. 3For this range the input is high impedance.
TIMING SPECIFICATIONS (–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) Parameter Symbol Min Typ Max Unit
Refer to Figures 11 and 12 Convert Pulsewidth t1 5 ns Time between Conversions t2 4 µs CNVST LOW to BUSY HIGH Delay t3 30 ns BUSY HIGH All Modes Except in t4 1.25 µs Master Serial Read after Convert Mode Aperture Delay t5 2 ns End of Conversion to BUSY LOW Delay t6 10 ns Conversion Time t7 1.25 µs Acquisition Time t8 2.75 µs RESET Pulsewidth t9 10 ns Refer to Figures 13, 14, 15, and 16 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay t10 1.25 µs DATA Valid to BUSY LOW Delay t11 20 ns Bus Access Request to DATA Valid t12 40 ns Bus Relinquish Time t13 5 15 ns Refer to Figures 17 and 18 (Master Serial Interface Modes)1 CS LOW to SYNC Valid Delay t14 10 ns CS LOW to Internal SCLK Valid Delay t15 10 ns CS LOW to SDOUT Delay t16 10 ns CNVST LOW to SYNC Delay (Read during Convert) t17 0.5 µs SYNC Asserted to SCLK First Edge Delay2 t18 4 ns Internal SCLK Period2 t19 25 40 ns Internal SCLK HIGH2 t20 15 ns Internal SCLK LOW2 t21 9.5 ns SDOUT Valid Setup Time2 t22 4.5 ns SDOUT Valid Hold Time2 t23 2 ns SCLK Last Edge to SYNC Delay2 t24 3 ns REV. B –3– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PulSAR Selection FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDERING GUIDE PIN FUNCTION DESCRIPTION DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Differential Nonlinearity Error (DNL) Full-Scale Error Bipolar Zero Error Unipolar Zero Error Spurious-Free Dynamic Range (SFDR) Effective Number of Bits (ENOB) Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR) Signal-to-(Noise + Distortion) Ratio (S/[N+D]) Aperture Delay Transient Response Typical Performance Characteristics CIRCUIT INFORMATION CONVERTER OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM Analog Inputs Driver Amplifier Choice Voltage Reference Input Scaler Reference Input (Bipolar Input Ranges) Power Supply POWER DISSIPATION CONVERSION CONTROL DIGITAL INTERFACE PARALLEL INTERFACE SERIAL INTERFACE MASTER SERIAL INTERFACE Internal Clock SLAVE SERIAL INTERFACE External Clock External Discontinuous Clock Data Read after Conversion External Clock Data Read during Conversion MICROPROCESSOR INTERFACING SPI Interface (MC68HC11) ADSP-21065L in Master Serial Interface APPLICATION HINTS Layout Evaluating the AD7663 Performance OUTLINE DIMENSIONS Revision History